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feinstr.c File Reference

#include "ki.h"
#include <stdio.h>
#include "fepublic.h"
#include "fehelper.h"
#include "festate.h"
#include "feinstr.h"

Go to the source code of this file.

Functions

void fp82_fma (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fpma (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fms (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fpms (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fnma (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fpnma (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f3, EM_fp_reg_specifier f4, EM_fp_reg_specifier f2)
void fp82_fcmp_eq (EM_state_type *ps, EM_opcode_ctype_type fctype, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_pred_reg_specifier p1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fcmp_lt (EM_state_type *ps, EM_opcode_ctype_type fctype, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_pred_reg_specifier p1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fcmp_le (EM_state_type *ps, EM_opcode_ctype_type fctype, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_pred_reg_specifier p1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fcmp_unord (EM_state_type *ps, EM_opcode_ctype_type fctype, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_pred_reg_specifier p1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_frcpa (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fprcpa (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_frsqrta (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f3)
void fp82_fprsqrta (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_pred_reg_specifier p2, EM_fp_reg_specifier f3)
void fp82_fmin (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fmax (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_famin (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_famax (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpmin (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpmax (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpamin (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpamax (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_eq (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_lt (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_le (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_unord (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_neq (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_nlt (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_nle (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fpcmp_ord (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2, EM_fp_reg_specifier f3)
void fp82_fcvt_fx (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fcvt_fxu (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fcvt_fx_trunc (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fcvt_fxu_trunc (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fpcvt_fx (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fpcvt_fxu (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fpcvt_fx_trunc (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
void fp82_fpcvt_fxu_trunc (EM_state_type *ps, EM_opcode_sf_type sf, EM_pred_reg_specifier qp, EM_fp_reg_specifier f1, EM_fp_reg_specifier f2)
INLINE void _fma (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fpma (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fms (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fpms (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fnma (EM_state_type *ps, EM_opcode_pc_type pc, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fpnma (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f3, EM_uint_t f4, EM_uint_t f2)
INLINE void _fcmp (EM_state_type *ps, EM_opcode_frel_type frel, EM_opcode_ctype_type fctype, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t p1, EM_uint_t p2, EM_uint_t f2, EM_uint_t f3)
INLINE void _frcpa (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t p2, EM_uint_t f2, EM_uint_t f3)
INLINE void _fprcpa (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t p2, EM_uint_t f2, EM_uint_t f3)
INLINE void _frsqrta (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t p2, EM_uint_t f3)
INLINE void _fprsqrta (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t p2, EM_uint_t f3)
INLINE void _fmin (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fmax (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _famin (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _famax (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fpmin (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fpmax (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fpamin (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fpamax (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fpcmp (EM_state_type *ps, EM_opcode_frel_type frel, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2, EM_uint_t f3)
INLINE void _fcvt_fx (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2)
INLINE void _fpcvt_fx (EM_state_type *ps, EM_opcode_sf_type sf, EM_uint_t qp, EM_uint_t f1, EM_uint_t f2)
EM_fp_reg_type fp_ieee_recip (EM_fp_reg_type den)
EM_fp_reg_type fp_ieee_recip_sqrt (EM_fp_reg_type root)


Function Documentation

INLINE void _famax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1558 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fminmax_exception_fault_check, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, PR, and fp_reg_struct::sign.

01564 { 01565 EM_uint_t tmp_isrcode; 01566 EM_fp_reg_type tmp_right, tmp_left; 01567 EM_tmp_fp_env_type tmp_fp_env; 01568 EM_boolean_t tmp_bool_res; 01569 01570 01571 /* EAS START */ 01572 if (PR[qp]) { 01573 fp_check_target_register(f1); 01574 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0) ) 01575 disabled_fp_register_fault(tmp_isrcode,0); 01576 01577 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01578 FR[f1] = NATVAL; 01579 } else { 01580 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01581 01582 if (fp_raise_fault(tmp_fp_env)) { 01583 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01584 return; // MACH 01585 } 01586 01587 tmp_right = fp_reg_read(FR[f2]); 01588 tmp_left = fp_reg_read(FR[f3]); 01589 tmp_right.sign = FP_SIGN_POSITIVE; 01590 tmp_left.sign = FP_SIGN_POSITIVE; 01591 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01592 01593 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01594 fp_update_fpsr(sf, tmp_fp_env); 01595 } 01596 fp_update_psr(f1); 01597 } 01598 /* EAS END */ 01599 }

INLINE void _famin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1511 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fminmax_exception_fault_check, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, PR, and fp_reg_struct::sign.

01517 { 01518 EM_uint_t tmp_isrcode; 01519 EM_fp_reg_type tmp_right, tmp_left; 01520 EM_tmp_fp_env_type tmp_fp_env; 01521 EM_boolean_t tmp_bool_res; 01522 01523 01524 /* EAS START */ 01525 if (PR[qp]) { 01526 fp_check_target_register(f1); 01527 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01528 disabled_fp_register_fault(tmp_isrcode,0); 01529 01530 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01531 FR[f1] = NATVAL; 01532 } else { 01533 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01534 if (fp_raise_fault(tmp_fp_env)) { 01535 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01536 return; // MACH 01537 } 01538 01539 tmp_left = fp_reg_read(FR[f2]); 01540 tmp_right = fp_reg_read(FR[f3]); 01541 tmp_left.sign = FP_SIGN_POSITIVE; 01542 tmp_right.sign = FP_SIGN_POSITIVE; 01543 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01544 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01545 01546 fp_update_fpsr(sf, tmp_fp_env); 01547 } 01548 fp_update_psr(f1); 01549 } 01550 /* EAS END */ 01551 }

INLINE void _fcmp EM_state_type ps,
EM_opcode_frel_type  frel,
EM_opcode_ctype_type  fctype,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  p1,
EM_uint_t  p2,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1023 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fcmp_exception_fault_check, fctypeUNC, fp_decode_fault, fp_equal(), fp_exception_fault, fp_is_natval(), fp_less_than(), fp_lesser_or_equal(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_unordered(), fp_update_fpsr, FR, frelEQ, frelGE, frelGT, frelLE, frelLT, frelNEQ, frelNGE, frelNGT, frelNLE, frelNLT, frelUNORD, illegal_operation_fault, and PR.

01032 { 01033 EM_uint_t tmp_isrcode; 01034 EM_fp_reg_type tmp_fr2, tmp_fr3; 01035 EM_tmp_fp_env_type tmp_fp_env; 01036 EM_boolean_t tmp_rel; 01037 01038 /* EAS START */ 01039 if (PR[qp]) { 01040 if(p1==p2) 01041 illegal_operation_fault(0); 01042 if (tmp_isrcode = fp_reg_disabled(f2, f3, 0, 0)) 01043 disabled_fp_register_fault(tmp_isrcode,0); 01044 01045 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01046 PR[p1] = 0; 01047 PR[p2] = 0; 01048 } else { 01049 fcmp_exception_fault_check(f2, f3, frel, sf, &tmp_fp_env); 01050 if (fp_raise_fault(tmp_fp_env)) { 01051 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01052 return; // MACH 01053 } 01054 01055 tmp_fr2 = fp_reg_read(FR[f2]); 01056 tmp_fr3 = fp_reg_read(FR[f3]); 01057 01058 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01059 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01060 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01061 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01062 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01063 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01064 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01065 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01066 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01067 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01068 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01069 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01070 01071 PR[p1] = tmp_rel; 01072 PR[p2] = !tmp_rel; 01073 fp_update_fpsr(sf, tmp_fp_env); 01074 } 01075 01076 } else { 01077 if (fctype == fctypeUNC) { 01078 if(p1==p2) 01079 illegal_operation_fault(0); 01080 PR[p1] = 0; 01081 PR[p2] = 0; 01082 } 01083 } 01084 /* EAS END */ 01085 }

INLINE void _fcvt_fx EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2
[static]
 

Definition at line 1908 of file feinstr.c.

References disabled_fp_register_fault, EM_int_t, EM_uint_t, fp_reg_struct::exponent, fcvt_exception_fault_check, fp_check_target_register, fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_rnd_to_int, fp_is_nan(), fp_is_natval(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read(), fp_U64_rsh, fp_update_fpsr, fp_update_psr, FR, PR, fp_reg_struct::sign, SIGNED_FORM, fp_reg_struct::significand, and TRUNC_FORM.

01913 { 01914 EM_uint_t tmp_isrcode; 01915 EM_fp_reg_type tmp_default_result, tmp_res; 01916 EM_tmp_fp_env_type tmp_fp_env; 01917 01918 /* EAS START */ 01919 if (PR[qp]) { 01920 fp_check_target_register(f1); 01921 if (tmp_isrcode = fp_reg_disabled(f1, f2, 0, 0)) 01922 disabled_fp_register_fault(tmp_isrcode,0); 01923 01924 if (fp_is_natval(FR[f2])) { 01925 FR[f1] = NATVAL; 01926 fp_update_psr(f1); 01927 } else { 01928 tmp_default_result = fcvt_exception_fault_check(f2, sf, 01929 SIGNED_FORM, TRUNC_FORM, &tmp_fp_env); 01930 01931 if (fp_raise_fault(tmp_fp_env)) { 01932 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01933 return; // MACH 01934 } 01935 01936 if (fp_is_nan(tmp_default_result)) { 01937 FR[f1].significand = INTEGER_INDEFINITE; 01938 FR[f1].exponent = FP_INTEGER_EXP; 01939 FR[f1].sign = FP_SIGN_POSITIVE; 01940 } else { 01941 tmp_res = fp_ieee_rnd_to_int(fp_reg_read(FR[f2]), &tmp_fp_env); 01942 if (tmp_res.exponent) 01943 tmp_res.significand = fp_U64_rsh( 01944 tmp_res.significand, FP_INTEGER_EXP - (EM_int_t)tmp_res.exponent); 01945 if (SIGNED_FORM && tmp_res.sign) 01946 tmp_res.significand = (~tmp_res.significand) + 1; 01947 01948 FR[f1].significand = tmp_res.significand; 01949 FR[f1].exponent = FP_INTEGER_EXP; 01950 FR[f1].sign = FP_SIGN_POSITIVE; 01951 } 01952 01953 fp_update_fpsr(sf, tmp_fp_env); 01954 fp_update_psr(f1); 01955 if (fp_raise_traps(tmp_fp_env)) 01956 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 01957 } 01958 } 01959 /* EAS END */ 01960 }

INLINE void _fma EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 648 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fma_exception_fault_check, fp_add(), fp_check_target_register, fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, and PR.

00656 { 00657 EM_uint_t tmp_isrcode; 00658 EM_fp_reg_type tmp_default_result; 00659 EM_tmp_fp_env_type tmp_fp_env; 00660 EM_fp_dp_type tmp_res; 00661 00662 /* EAS START */ 00663 if (PR[qp]) { 00664 fp_check_target_register(f1); 00665 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00666 disabled_fp_register_fault(tmp_isrcode,0); 00667 00668 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00669 FR[f1] = NATVAL; 00670 fp_update_psr(f1); 00671 } else { 00672 tmp_default_result = fma_exception_fault_check(f2, f3, f4, 00673 pc, sf, &tmp_fp_env); 00674 if (fp_raise_fault(tmp_fp_env)) { 00675 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00676 return; // MACH 00677 } 00678 00679 if (fp_is_nan_or_inf(tmp_default_result)) { 00680 FR[f1] = tmp_default_result; 00681 } else { 00682 tmp_res = fp_mul(fp_reg_read(FR[f3]), 00683 fp_reg_read(FR[f4])); 00684 if (f2 != 0) 00685 tmp_res = fp_add(tmp_res, fp_reg_read(FR[f2]), tmp_fp_env); 00686 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00687 } 00688 00689 fp_update_fpsr(sf, tmp_fp_env); 00690 fp_update_psr(f1); 00691 if (fp_raise_traps(tmp_fp_env)) 00692 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00693 } 00694 } 00695 /* EAS END */ 00696 }

INLINE void _fmax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1470 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fminmax_exception_fault_check, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, and PR.

01476 { 01477 EM_uint_t tmp_isrcode; 01478 EM_tmp_fp_env_type tmp_fp_env; 01479 EM_boolean_t tmp_bool_res; 01480 01481 /* EAS START */ 01482 if (PR[qp]) { 01483 fp_check_target_register(f1); 01484 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01485 disabled_fp_register_fault(tmp_isrcode,0); 01486 01487 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01488 FR[f1] = NATVAL; 01489 } else { 01490 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01491 if (fp_raise_fault(tmp_fp_env)) { 01492 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01493 return; // MACH 01494 } 01495 01496 tmp_bool_res = fp_less_than(fp_reg_read(FR[f3]), fp_reg_read(FR[f2])); 01497 FR[f1] = (tmp_bool_res ? FR[f2] : FR[f3]); 01498 01499 fp_update_fpsr(sf, tmp_fp_env); 01500 } 01501 fp_update_psr(f1); 01502 } 01503 /* EAS END */ 01504 }

INLINE void _fmin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1428 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fminmax_exception_fault_check, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, and PR.

01434 { 01435 EM_uint_t tmp_isrcode; 01436 EM_tmp_fp_env_type tmp_fp_env; 01437 EM_boolean_t tmp_bool_res; 01438 01439 /* EAS START */ 01440 if (PR[qp]) { 01441 fp_check_target_register(f1); 01442 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01443 disabled_fp_register_fault(tmp_isrcode,0); 01444 01445 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01446 FR[f1] = NATVAL; 01447 } else { 01448 fminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01449 01450 if (fp_raise_fault(tmp_fp_env)) { 01451 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01452 return; // MACH 01453 } 01454 01455 tmp_bool_res = fp_less_than(fp_reg_read(FR[f2]), fp_reg_read(FR[f3])); 01456 FR[f1] = tmp_bool_res ? FR[f2] : FR[f3]; 01457 01458 fp_update_fpsr(sf, tmp_fp_env); 01459 } 01460 fp_update_psr(f1); 01461 } 01462 /* EAS END */ 01463 }

INLINE void _fms EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 770 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fms_fnma_exception_fault_check, fp_add(), fp_check_target_register, fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, PR, and fp_reg_struct::sign.

00778 { 00779 EM_uint_t tmp_isrcode; 00780 EM_fp_reg_type tmp_fr2, tmp_default_result; 00781 EM_fp_dp_type tmp_res; 00782 EM_tmp_fp_env_type tmp_fp_env; 00783 00784 /* EAS START */ 00785 if (PR[qp]) { 00786 fp_check_target_register(f1); 00787 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00788 disabled_fp_register_fault(tmp_isrcode,0); 00789 00790 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00791 FR[f1] = NATVAL; 00792 fp_update_psr(f1); 00793 } else { 00794 tmp_default_result = fms_fnma_exception_fault_check(f2, f3, f4, 00795 pc, sf, &tmp_fp_env); 00796 00797 if (fp_raise_fault(tmp_fp_env)) { 00798 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00799 return; // MACH 00800 } 00801 00802 if (fp_is_nan_or_inf(tmp_default_result)) { 00803 FR[f1] = tmp_default_result; 00804 } else { 00805 tmp_res = fp_mul(fp_reg_read(FR[f3]), fp_reg_read(FR[f4])); 00806 tmp_fr2 = fp_reg_read(FR[f2]); 00807 tmp_fr2.sign = !tmp_fr2.sign; 00808 if (f2 != 0) 00809 tmp_res = fp_add(tmp_res, tmp_fr2, tmp_fp_env); 00810 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00811 } 00812 00813 fp_update_fpsr(sf, tmp_fp_env); 00814 fp_update_psr(f1); 00815 if (fp_raise_traps(tmp_fp_env)) 00816 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00817 } 00818 } 00819 /* EAS END */ 00820 }

INLINE void _fnma EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 900 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fms_fnma_exception_fault_check, fp_add(), fp_check_target_register, fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, PR, and fp_dp_struct::sign.

00908 { 00909 EM_uint_t tmp_isrcode; 00910 EM_fp_reg_type tmp_default_result; 00911 EM_tmp_fp_env_type tmp_fp_env; 00912 EM_fp_dp_type tmp_res; 00913 00914 /* EAS START */ 00915 if (PR[qp]) { 00916 fp_check_target_register(f1); 00917 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00918 disabled_fp_register_fault(tmp_isrcode,0); 00919 00920 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00921 FR[f1] = NATVAL; 00922 fp_update_psr(f1); 00923 } else { 00924 tmp_default_result = fms_fnma_exception_fault_check(f2, f3, f4, 00925 pc, sf, &tmp_fp_env); 00926 00927 if (fp_raise_fault(tmp_fp_env)) { 00928 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00929 return; // MACH 00930 } 00931 00932 if (fp_is_nan_or_inf(tmp_default_result)) { 00933 FR[f1] = tmp_default_result; 00934 } else { 00935 tmp_res = fp_mul(fp_reg_read(FR[f3]), fp_reg_read(FR[f4])); 00936 tmp_res.sign = !tmp_res.sign; 00937 if (f2 != 0) 00938 tmp_res = fp_add(tmp_res, fp_reg_read(FR[f2]), tmp_fp_env); 00939 FR[f1] = fp_ieee_round(tmp_res, &tmp_fp_env); 00940 } 00941 00942 fp_update_fpsr(sf, tmp_fp_env); 00943 fp_update_psr(f1); 00944 if (fp_raise_traps(tmp_fp_env)) 00945 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00946 } 00947 } 00948 /* EAS END */ 00949 }

INLINE void _fpamax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1767 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpminmax_exception_fault_check, FR, and PR.

01773 { 01774 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01775 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01776 EM_tmp_fp_env_type tmp_fp_env; 01777 EM_boolean_t tmp_bool_res; 01778 01779 01780 /* EAS START */ 01781 if (PR[qp]) { 01782 fp_check_target_register(f1); 01783 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01784 disabled_fp_register_fault(tmp_isrcode,0); 01785 01786 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01787 FR[f1] = NATVAL; 01788 } else { 01789 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01790 if (fp_raise_fault(tmp_fp_env)) { 01791 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01792 return; // MACH 01793 } 01794 01795 01796 tmp_fr2 = tmp_right = fp_reg_read_hi(f2); 01797 tmp_fr3 = tmp_left = fp_reg_read_hi(f3); 01798 tmp_right.sign = FP_SIGN_POSITIVE; 01799 tmp_left.sign = FP_SIGN_POSITIVE; 01800 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01801 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01802 01803 01804 tmp_fr2 = tmp_right = fp_reg_read_lo(f2); 01805 tmp_fr3 = tmp_left = fp_reg_read_lo(f3); 01806 tmp_right.sign = FP_SIGN_POSITIVE; 01807 tmp_left.sign = FP_SIGN_POSITIVE; 01808 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01809 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01810 01811 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01812 FR[f1].exponent = FP_INTEGER_EXP; 01813 FR[f1].sign = FP_SIGN_POSITIVE; 01814 01815 fp_update_fpsr(sf, tmp_fp_env); 01816 } 01817 fp_update_psr(f1); 01818 } 01819 /* EAS END */ 01820 }

INLINE void _fpamin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1708 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpminmax_exception_fault_check, FR, and PR.

01714 { 01715 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01716 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01717 EM_tmp_fp_env_type tmp_fp_env; 01718 EM_boolean_t tmp_bool_res; 01719 01720 /* EAS START */ 01721 if (PR[qp]) { 01722 fp_check_target_register(f1); 01723 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01724 disabled_fp_register_fault(tmp_isrcode,0); 01725 01726 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01727 FR[f1] = NATVAL; 01728 } else { 01729 fpminmax_exception_fault_check(f2,f3, sf, &tmp_fp_env); 01730 if(fp_raise_fault(tmp_fp_env)) { 01731 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01732 return; // MACH 01733 } 01734 01735 01736 tmp_fr2 = tmp_left = fp_reg_read_hi(f2); 01737 tmp_fr3 = tmp_right = fp_reg_read_hi(f3); 01738 tmp_left.sign = FP_SIGN_POSITIVE; 01739 tmp_right.sign = FP_SIGN_POSITIVE; 01740 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01741 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2 : tmp_fr3); 01742 01743 01744 tmp_fr2 = tmp_left = fp_reg_read_lo(f2); 01745 tmp_fr3 = tmp_right = fp_reg_read_lo(f3); 01746 tmp_left.sign = FP_SIGN_POSITIVE; 01747 tmp_right.sign = FP_SIGN_POSITIVE; 01748 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01749 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01750 01751 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01752 FR[f1].exponent = FP_INTEGER_EXP; 01753 FR[f1].sign = FP_SIGN_POSITIVE; 01754 01755 fp_update_fpsr(sf, tmp_fp_env); 01756 } 01757 fp_update_psr(f1); 01758 } 01759 /* EAS END */ 01760 }

INLINE void _fpcmp EM_state_type ps,
EM_opcode_frel_type  frel,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1826 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_equal(), fp_exception_fault, fp_is_natval(), fp_less_than(), fp_lesser_or_equal(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_unordered(), fp_update_fpsr, fp_update_psr, fpcmp_exception_fault_check, FR, frelEQ, frelGE, frelGT, frelLE, frelLT, frelNEQ, frelNGE, frelNGT, frelNLE, frelNLT, frelUNORD, and PR.

01833 { 01834 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01835 EM_fp_reg_type tmp_fr2, tmp_fr3; 01836 EM_tmp_fp_env_type tmp_fp_env; 01837 EM_boolean_t tmp_rel; 01838 01839 /* EAS START */ 01840 if (PR[qp]) { 01841 fp_check_target_register(f1); 01842 if(tmp_isrcode = fp_reg_disabled(f1, f2,f3, 0)) 01843 disabled_fp_register_fault(tmp_isrcode,0); 01844 01845 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) ) { 01846 FR[f1] = NATVAL; 01847 } else { 01848 fpcmp_exception_fault_check(f2, f3, frel, sf, &tmp_fp_env); 01849 01850 if (fp_raise_fault(tmp_fp_env)) { 01851 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01852 return; // MACH 01853 } 01854 01855 01856 tmp_fr2 = fp_reg_read_hi(f2); 01857 tmp_fr3 = fp_reg_read_hi(f3); 01858 01859 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01860 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01861 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01862 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01863 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01864 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01865 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01866 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01867 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01868 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01869 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01870 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01871 01872 tmp_res_hi = (tmp_rel ? 0xFFFFFFFF : 0x00000000); 01873 01874 01875 tmp_fr2 = fp_reg_read_lo(f2); 01876 tmp_fr3 = fp_reg_read_lo(f3); 01877 01878 if (frel == frelEQ) tmp_rel = fp_equal(tmp_fr2, tmp_fr3); 01879 else if (frel == frelLT) tmp_rel = fp_less_than(tmp_fr2, tmp_fr3); 01880 else if (frel == frelLE) tmp_rel = fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01881 else if (frel == frelGT) tmp_rel = fp_less_than(tmp_fr3, tmp_fr2); 01882 else if (frel == frelGE) tmp_rel = fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01883 else if (frel == frelUNORD) tmp_rel = fp_unordered(tmp_fr2, tmp_fr3); 01884 else if (frel == frelNEQ) tmp_rel = !fp_equal(tmp_fr2, tmp_fr3); 01885 else if (frel == frelNLT) tmp_rel = !fp_less_than(tmp_fr2, tmp_fr3); 01886 else if (frel == frelNLE) tmp_rel = !fp_lesser_or_equal(tmp_fr2, tmp_fr3); 01887 else if (frel == frelNGT) tmp_rel = !fp_less_than(tmp_fr3, tmp_fr2); 01888 else if (frel == frelNGE) tmp_rel = !fp_lesser_or_equal(tmp_fr3, tmp_fr2); 01889 else tmp_rel = !fp_unordered(tmp_fr2, tmp_fr3); 01890 01891 tmp_res_lo = (tmp_rel ? 0xFFFFFFFF : 0x00000000); 01892 01893 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01894 FR[f1].exponent = FP_INTEGER_EXP; 01895 FR[f1].sign = FP_SIGN_POSITIVE; 01896 01897 fp_update_fpsr(sf, tmp_fp_env); 01898 } 01899 fp_update_psr(f1); 01900 } 01901 /* EAS END */ 01902 }

INLINE void _fpcvt_fx EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2
[static]
 

Definition at line 1966 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_reg_struct::exponent, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_extract_bits(), fp_ieee_rnd_to_int_sp, fp_is_nan(), fp_is_natval(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_U64_rsh, fp_update_fpsr, fp_update_psr, fpcvt_exception_fault_check, FR, pair_fp_reg_struct::hi, high, pair_fp_reg_struct::lo, low, PR, fp_reg_struct::sign, SIGNED_FORM, fp_reg_struct::significand, and TRUNC_FORM.

01971 { 01972 EM_uint_t tmp_isrcode, tmp_res_lo, tmp_res_hi; 01973 EM_pair_fp_reg_type tmp_default_result_pair; 01974 EM_fp_reg_type tmp_res; 01975 EM_tmp_fp_env_type tmp_fp_env; 01976 01977 /* EAS START */ 01978 if (PR[qp]) { 01979 fp_check_target_register(f1); 01980 if (tmp_isrcode = fp_reg_disabled(f1, f2, 0, 0)) 01981 disabled_fp_register_fault(tmp_isrcode,0); 01982 01983 if (fp_is_natval(FR[f2]) ) { 01984 FR[f1] = NATVAL; 01985 fp_update_psr(f1); 01986 } else { 01987 tmp_default_result_pair = fpcvt_exception_fault_check(f2, sf, 01988 SIGNED_FORM, TRUNC_FORM, &tmp_fp_env); 01989 if (fp_raise_fault(tmp_fp_env)) { 01990 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01991 return; // MACH 01992 } 01993 01994 if (fp_is_nan(tmp_default_result_pair.hi)) { 01995 tmp_res_hi = INTEGER_INDEFINITE_32_BIT; 01996 } else { 01997 tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_hi(f2), high, &tmp_fp_env); 01998 if (tmp_res.exponent) 01999 tmp_res.significand = fp_U64_rsh( 02000 tmp_res.significand, (FP_INTEGER_EXP - tmp_res.exponent)); 02001 if (SIGNED_FORM && tmp_res.sign) 02002 tmp_res.significand = (~tmp_res.significand) + 1; 02003 02004 tmp_res_hi = fp_extract_bits(tmp_res.significand, 31, 0); 02005 } 02006 02007 if (fp_is_nan(tmp_default_result_pair.lo)) { 02008 tmp_res_lo = INTEGER_INDEFINITE_32_BIT; 02009 } else { 02010 tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_lo(f2), low, &tmp_fp_env); 02011 if (tmp_res.exponent) 02012 tmp_res.significand = fp_U64_rsh( 02013 tmp_res.significand,(FP_INTEGER_EXP - tmp_res.exponent)); 02014 if (SIGNED_FORM && tmp_res.sign) 02015 tmp_res.significand = (~tmp_res.significand) + 1; 02016 02017 tmp_res_lo = fp_extract_bits(tmp_res.significand, 31, 0); 02018 } 02019 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 02020 FR[f1].exponent = FP_INTEGER_EXP; 02021 FR[f1].sign = FP_SIGN_POSITIVE; 02022 02023 fp_update_fpsr(sf, tmp_fp_env); 02024 fp_update_psr(f1); 02025 if (fp_raise_traps(tmp_fp_env)) 02026 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 02027 } 02028 } 02029 /* EAS END */ 02030 }

INLINE void _fpma EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 703 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_add(), fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round_sp, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpma_exception_fault_check, FR, pair_fp_reg_struct::hi, high, pair_fp_reg_struct::lo, low, and PR.

00710 { 00711 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00712 EM_pair_fp_reg_type tmp_default_result_pair; 00713 EM_tmp_fp_env_type tmp_fp_env; 00714 EM_fp_dp_type tmp_res; 00715 00716 /* EAS START */ 00717 if (PR[qp]) { 00718 fp_check_target_register(f1); 00719 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00720 disabled_fp_register_fault(tmp_isrcode,0); 00721 00722 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00723 FR[f1] = NATVAL; 00724 fp_update_psr(f1); 00725 } else { 00726 tmp_default_result_pair = fpma_exception_fault_check(f2, 00727 f3, f4, sf, &tmp_fp_env); 00728 00729 if (fp_raise_fault(tmp_fp_env)) { 00730 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00731 return; // MACH 00732 } 00733 00734 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00735 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00736 } else { 00737 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00738 if (f2 != 0) 00739 tmp_res = fp_add(tmp_res, fp_reg_read_hi(f2), tmp_fp_env); 00740 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00741 } 00742 00743 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00744 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00745 } else { 00746 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00747 if (f2 != 0) 00748 tmp_res = fp_add(tmp_res, fp_reg_read_lo(f2), tmp_fp_env); 00749 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 00750 } 00751 00752 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 00753 FR[f1].exponent = FP_INTEGER_EXP; 00754 FR[f1].sign = FP_SIGN_POSITIVE; 00755 00756 fp_update_fpsr(sf, tmp_fp_env); 00757 fp_update_psr(f1); 00758 if (fp_raise_traps(tmp_fp_env)) 00759 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00760 } 00761 } 00762 /* EAS END */ 00763 }

INLINE void _fpmax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1657 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpminmax_exception_fault_check, FR, and PR.

01663 { 01664 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01665 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01666 EM_tmp_fp_env_type tmp_fp_env; 01667 EM_boolean_t tmp_bool_res; 01668 01669 /* EAS START */ 01670 if (PR[qp]) { 01671 fp_check_target_register(f1); 01672 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01673 disabled_fp_register_fault(tmp_isrcode,0); 01674 01675 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01676 FR[f1] = NATVAL; 01677 } else { 01678 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01679 if (fp_raise_fault(tmp_fp_env)) { 01680 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01681 return; // MACH 01682 } 01683 01684 tmp_fr2 = tmp_right = fp_reg_read_hi(f2); 01685 tmp_fr3 = tmp_left = fp_reg_read_hi(f3); 01686 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01687 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2 : tmp_fr3); 01688 01689 tmp_fr2 = tmp_right = fp_reg_read_lo(f2); 01690 tmp_fr3 = tmp_left = fp_reg_read_lo(f3); 01691 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01692 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01693 01694 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01695 FR[f1].exponent = FP_INTEGER_EXP; 01696 FR[f1].sign = FP_SIGN_POSITIVE; 01697 fp_update_fpsr(sf, tmp_fp_env); 01698 } 01699 fp_update_psr(f1); 01700 } 01701 /* EAS END */ 01702 }

INLINE void _fpmin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1605 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_is_natval(), fp_less_than(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpminmax_exception_fault_check, FR, and PR.

01611 { 01612 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01613 EM_fp_reg_type tmp_right, tmp_left, tmp_fr2, tmp_fr3; 01614 EM_tmp_fp_env_type tmp_fp_env; 01615 EM_boolean_t tmp_bool_res; 01616 01617 /* EAS START */ 01618 if (PR[qp]) { 01619 fp_check_target_register(f1); 01620 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01621 disabled_fp_register_fault(tmp_isrcode,0); 01622 01623 if (fp_is_natval(FR[f2] ) || fp_is_natval(FR[f3]) ) { 01624 FR[f1] = NATVAL; 01625 } else { 01626 fpminmax_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01627 if (fp_raise_fault(tmp_fp_env)) { 01628 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01629 return; // MACH 01630 } 01631 01632 tmp_fr2 = tmp_left = fp_reg_read_hi(f2); 01633 tmp_fr3 = tmp_right = fp_reg_read_hi(f3); 01634 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01635 tmp_res_hi = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01636 01637 tmp_fr2 = tmp_left = fp_reg_read_lo(f2); 01638 tmp_fr3 = tmp_right = fp_reg_read_lo(f3); 01639 tmp_bool_res = fp_less_than(tmp_left, tmp_right); 01640 tmp_res_lo = fp_single(tmp_bool_res ? tmp_fr2: tmp_fr3); 01641 01642 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01643 FR[f1].exponent = FP_INTEGER_EXP; 01644 FR[f1].sign = FP_SIGN_POSITIVE; 01645 01646 fp_update_fpsr(sf, tmp_fp_env); 01647 } 01648 fp_update_psr(f1); 01649 } 01650 /* EAS END */ 01651 }

INLINE void _fpms EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 827 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_add(), fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round_sp, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpms_fpnma_exception_fault_check, FR, pair_fp_reg_struct::hi, high, pair_fp_reg_struct::lo, low, PR, and fp_reg_struct::sign.

00834 { 00835 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00836 EM_pair_fp_reg_type tmp_default_result_pair; 00837 EM_fp_reg_type tmp_sub; 00838 EM_fp_dp_type tmp_res; 00839 EM_tmp_fp_env_type tmp_fp_env; 00840 00841 /* EAS START */ 00842 if (PR[qp]) { 00843 fp_check_target_register(f1); 00844 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00845 disabled_fp_register_fault(tmp_isrcode,0); 00846 00847 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00848 FR[f1] = NATVAL; 00849 fp_update_psr(f1); 00850 } else { 00851 tmp_default_result_pair = fpms_fpnma_exception_fault_check(f2, f3, f4, 00852 sf, &tmp_fp_env); 00853 if (fp_raise_fault(tmp_fp_env)) { 00854 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00855 return; // MACH 00856 } 00857 00858 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00859 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00860 } else { 00861 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00862 if (f2 != 0) { 00863 tmp_sub = fp_reg_read_hi(f2); 00864 tmp_sub.sign = !tmp_sub.sign; 00865 tmp_res = fp_add(tmp_res, tmp_sub, tmp_fp_env); 00866 } 00867 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00868 } 00869 00870 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00871 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00872 } else { 00873 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00874 if (f2 != 0) { 00875 tmp_sub = fp_reg_read_lo(f2); 00876 tmp_sub.sign = !tmp_sub.sign; 00877 tmp_res = fp_add(tmp_res, tmp_sub, tmp_fp_env); 00878 } 00879 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 00880 } 00881 00882 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 00883 FR[f1].exponent = FP_INTEGER_EXP; 00884 FR[f1].sign = FP_SIGN_POSITIVE; 00885 00886 fp_update_fpsr(sf, tmp_fp_env); 00887 fp_update_psr(f1); 00888 if (fp_raise_traps(tmp_fp_env)) 00889 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 00890 } 00891 } 00892 /* EAS END */ 00893 }

INLINE void _fpnma EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  f3,
EM_uint_t  f4,
EM_uint_t  f2
[static]
 

Definition at line 955 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_add(), fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_decode_trap, fp_exception_fault, fp_exception_trap, fp_ieee_round_sp, fp_is_nan_or_inf(), fp_is_natval(), fp_mul(), fp_raise_fault, fp_raise_traps, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fpms_fpnma_exception_fault_check, FR, pair_fp_reg_struct::hi, high, pair_fp_reg_struct::lo, low, PR, and fp_dp_struct::sign.

00962 { 00963 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 00964 EM_pair_fp_reg_type tmp_default_result_pair; 00965 EM_tmp_fp_env_type tmp_fp_env; 00966 EM_fp_dp_type tmp_res; 00967 00968 /* EAS START */ 00969 if (PR[qp]) { 00970 fp_check_target_register(f1); 00971 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, f4)) 00972 disabled_fp_register_fault(tmp_isrcode,0); 00973 00974 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3]) || fp_is_natval(FR[f4])) { 00975 FR[f1] = NATVAL; 00976 fp_update_psr(f1); 00977 } else { 00978 tmp_default_result_pair = fpms_fpnma_exception_fault_check(f2, f3, f4, 00979 sf, &tmp_fp_env); 00980 if (fp_raise_fault(tmp_fp_env)) { 00981 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 00982 return; // MACH 00983 } 00984 00985 if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) { 00986 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 00987 } else { 00988 tmp_res = fp_mul(fp_reg_read_hi(f3), fp_reg_read_hi(f4)); 00989 tmp_res.sign = !tmp_res.sign; 00990 if (f2 != 0) 00991 tmp_res = fp_add(tmp_res, fp_reg_read_hi(f2), tmp_fp_env); 00992 tmp_res_hi = fp_ieee_round_sp(tmp_res, high, &tmp_fp_env); 00993 } 00994 00995 if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) { 00996 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 00997 } else { 00998 tmp_res = fp_mul(fp_reg_read_lo(f3), fp_reg_read_lo(f4)); 00999 tmp_res.sign = !tmp_res.sign; 01000 if (f2 != 0) 01001 tmp_res = fp_add(tmp_res, fp_reg_read_lo(f2), tmp_fp_env); 01002 tmp_res_lo = fp_ieee_round_sp(tmp_res, low, &tmp_fp_env); 01003 } 01004 01005 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01006 FR[f1].exponent = FP_INTEGER_EXP; 01007 FR[f1].sign = FP_SIGN_POSITIVE; 01008 01009 fp_update_fpsr(sf, tmp_fp_env); 01010 fp_update_psr(f1); 01011 if (fp_raise_traps(tmp_fp_env)) 01012 fp_exception_trap(fp_decode_trap(tmp_fp_env)); 01013 } 01014 } 01015 /* EAS END */ 01016 }

INLINE void _fprcpa EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  p2,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1159 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_ieee_recip(), fp_is_finite(), fp_is_inf(), fp_is_nan_or_inf(), fp_is_natval(), fp_is_zero(), fp_normalize(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fprcpa_exception_fault_check, FR, pair_fp_reg_struct::hi, EM_limits_check_fprcpa_struct::hi_fr2_or_quot, EM_limits_check_fprcpa_struct::hi_fr3, pair_fp_reg_struct::lo, EM_limits_check_fprcpa_struct::lo_fr2_or_quot, EM_limits_check_fprcpa_struct::lo_fr3, PR, and fp_reg_struct::sign.

01166 { 01167 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01168 EM_pair_fp_reg_type tmp_default_result_pair; 01169 EM_fp_reg_type tmp_res, num, den; 01170 EM_boolean_t tmp_pred_hi, tmp_pred_lo; 01171 EM_tmp_fp_env_type tmp_fp_env; 01172 EM_limits_check_fprcpa limits_check = {0,0,0,0}; 01173 01174 /* EAS START */ 01175 if (PR[qp]) { 01176 fp_check_target_register(f1); 01177 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01178 disabled_fp_register_fault(tmp_isrcode,0); 01179 01180 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01181 FR[f1] = NATVAL; 01182 PR[p2] = 0; 01183 } else { 01184 tmp_default_result_pair = fprcpa_exception_fault_check(f2, f3, sf, 01185 &tmp_fp_env, &limits_check); 01186 if (fp_raise_fault(tmp_fp_env)) { 01187 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01188 return; // MACH 01189 } 01190 01191 if (fp_is_nan_or_inf(tmp_default_result_pair.hi) || limits_check.hi_fr3) { 01192 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 01193 tmp_pred_hi = 0; 01194 01195 } else { 01196 num = fp_normalize(fp_reg_read_hi(f2)); 01197 den = fp_normalize(fp_reg_read_hi(f3)); 01198 01199 if (fp_is_inf(num) && fp_is_finite(den)) { 01200 tmp_res = FP_INFINITY; 01201 tmp_res.sign = num.sign ^ den.sign; 01202 tmp_pred_hi = 0; 01203 01204 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01205 tmp_res = FP_ZERO; 01206 tmp_res.sign = num.sign ^ den.sign; 01207 tmp_pred_hi = 0; 01208 01209 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01210 tmp_res = FP_ZERO; 01211 tmp_res.sign = num.sign ^ den.sign; 01212 tmp_pred_hi = 0; 01213 01214 } else { 01215 tmp_res = fp_ieee_recip(den); 01216 if (limits_check.hi_fr2_or_quot) { 01217 tmp_pred_hi = 0; 01218 } else { 01219 tmp_pred_hi = 1; 01220 } 01221 } 01222 tmp_res_hi = fp_single(tmp_res); 01223 } 01224 01225 01226 if (fp_is_nan_or_inf(tmp_default_result_pair.lo) || limits_check.lo_fr3) { 01227 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 01228 tmp_pred_lo = 0; 01229 } else { 01230 num = fp_normalize(fp_reg_read_lo(f2)); 01231 den = fp_normalize(fp_reg_read_lo(f3)); 01232 01233 if (fp_is_inf(num) && fp_is_finite(den)) { 01234 tmp_res = FP_INFINITY; 01235 tmp_res.sign = num.sign ^ den.sign; 01236 tmp_pred_lo = 0; 01237 01238 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01239 tmp_res = FP_ZERO; 01240 tmp_res.sign = num.sign ^ den.sign; 01241 tmp_pred_lo = 0; 01242 01243 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01244 tmp_res = FP_ZERO; 01245 tmp_res.sign = num.sign ^ den.sign; 01246 tmp_pred_lo = 0; 01247 01248 } else { 01249 tmp_res = fp_ieee_recip(den); 01250 if (limits_check.lo_fr2_or_quot) { 01251 tmp_pred_lo = 0; 01252 } else { 01253 tmp_pred_lo = 1; 01254 } 01255 } 01256 tmp_res_lo = fp_single(tmp_res); 01257 } 01258 01259 FR[f1].significand = fp_concatenate(tmp_res_hi, tmp_res_lo); 01260 FR[f1].exponent = FP_INTEGER_EXP; 01261 FR[f1].sign = FP_SIGN_POSITIVE; 01262 PR[p2] = tmp_pred_hi && tmp_pred_lo; 01263 01264 fp_update_fpsr(sf, tmp_fp_env); 01265 } 01266 fp_update_psr(f1); 01267 } else { 01268 PR[p2] = 0; /* unconditional semantics */ 01269 } 01270 /* EAS END */ 01271 }

INLINE void _fprsqrta EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  p2,
EM_uint_t  f3
[static]
 

Definition at line 1333 of file feinstr.c.

References disabled_fp_register_fault, EM_boolean_t, EM_uint_t, fp_check_target_register, fp_concatenate(), fp_decode_fault, fp_exception_fault, fp_ieee_recip_sqrt(), fp_is_nan(), fp_is_natval(), fp_is_pos_inf(), fp_is_zero(), fp_normalize(), fp_raise_fault, fp_reg_disabled, fp_reg_read_hi, fp_reg_read_lo, fp_single(), fp_update_fpsr, fp_update_psr, fprsqrta_exception_fault_check, FR, EM_limits_check_fprsqrta_struct::hi, pair_fp_reg_struct::hi, EM_limits_check_fprsqrta_struct::lo, pair_fp_reg_struct::lo, PR, and fp_reg_struct::sign.

01339 { 01340 EM_uint_t tmp_isrcode, tmp_res_hi, tmp_res_lo; 01341 EM_pair_fp_reg_type tmp_default_result_pair; 01342 EM_fp_reg_type tmp_res, tmp_fr3; 01343 EM_boolean_t tmp_pred_hi, tmp_pred_lo; 01344 EM_tmp_fp_env_type tmp_fp_env; 01345 EM_limits_check_fprsqrta limits_check = {0, 0}; 01346 01347 /* EAS START */ 01348 if (PR[qp]) { 01349 fp_check_target_register(f1); 01350 if (tmp_isrcode = fp_reg_disabled(f1, f3, 0, 0)) 01351 disabled_fp_register_fault(tmp_isrcode,0); 01352 01353 if( fp_is_natval(FR[f3])) { 01354 PR[p2] = 0; 01355 FR[f1] = NATVAL; 01356 } else { 01357 tmp_default_result_pair = fprsqrta_exception_fault_check(f3, sf, 01358 &tmp_fp_env, &limits_check); 01359 if(fp_raise_fault(tmp_fp_env)) { 01360 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01361 return; // MACH 01362 } 01363 01364 if (fp_is_nan(tmp_default_result_pair.hi) ) { 01365 tmp_res_hi = fp_single(tmp_default_result_pair.hi); 01366 tmp_pred_hi = 0; 01367 } else { 01368 tmp_fr3 = fp_normalize(fp_reg_read_hi(f3)); 01369 if (fp_is_zero(tmp_fr3)) { 01370 tmp_res = FP_INFINITY; 01371 tmp_res.sign = tmp_fr3.sign; 01372 tmp_pred_hi = 0; 01373 } else if (fp_is_pos_inf(tmp_fr3)) { 01374 tmp_res = FP_ZERO; 01375 tmp_pred_hi = 0; 01376 } else { 01377 tmp_res = fp_ieee_recip_sqrt(tmp_fr3); 01378 if (limits_check.hi) 01379 tmp_pred_hi = 0; 01380 else 01381 tmp_pred_hi = 1; 01382 } 01383 tmp_res_hi = fp_single(tmp_res); 01384 } 01385 01386 01387 if (fp_is_nan(tmp_default_result_pair.lo) ) { 01388 tmp_res_lo = fp_single(tmp_default_result_pair.lo); 01389 tmp_pred_lo = 0; 01390 } else { 01391 tmp_fr3 = fp_normalize(fp_reg_read_lo(f3)); 01392 if (fp_is_zero(tmp_fr3)) { 01393 tmp_res = FP_INFINITY; 01394 tmp_res.sign = tmp_fr3.sign; 01395 tmp_pred_lo = 0; 01396 } else if (fp_is_pos_inf(tmp_fr3)) { 01397 tmp_res = FP_ZERO; 01398 tmp_pred_lo = 0; 01399 } else { 01400 tmp_res = fp_ieee_recip_sqrt(tmp_fr3); 01401 if (limits_check.lo) 01402 tmp_pred_lo = 0; 01403 else 01404 tmp_pred_lo = 1; 01405 } 01406 tmp_res_lo = fp_single(tmp_res); 01407 } 01408 01409 FR[f1].significand = fp_concatenate(tmp_res_hi,tmp_res_lo); 01410 FR[f1].exponent = FP_INTEGER_EXP; 01411 FR[f1].sign = FP_SIGN_POSITIVE; 01412 PR[p2] = tmp_pred_hi & tmp_pred_lo; 01413 01414 fp_update_fpsr(sf, tmp_fp_env); 01415 } 01416 fp_update_psr(f1); 01417 } else { 01418 PR[p2] = 0; 01419 } 01420 /* EAS END */ 01421 }

INLINE void _frcpa EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  p2,
EM_uint_t  f2,
EM_uint_t  f3
[static]
 

Definition at line 1091 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_ieee_recip(), fp_is_finite(), fp_is_inf(), fp_is_nan_or_inf(), fp_is_natval(), fp_is_zero(), fp_normalize(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, frcpa_exception_fault_check, PR, and fp_reg_struct::sign.

01098 { 01099 EM_uint_t tmp_isrcode; 01100 EM_fp_reg_type tmp_default_result, num, den; 01101 EM_tmp_fp_env_type tmp_fp_env; 01102 01103 /* EAS START */ 01104 if (PR[qp]) { 01105 fp_check_target_register(f1); 01106 if (tmp_isrcode = fp_reg_disabled(f1, f2, f3, 0)) 01107 disabled_fp_register_fault(tmp_isrcode,0); 01108 01109 if (fp_is_natval(FR[f2]) || fp_is_natval(FR[f3])) { 01110 FR[f1] = NATVAL; 01111 PR[p2] = 0; 01112 } else { 01113 tmp_default_result = frcpa_exception_fault_check(f2, f3, sf, &tmp_fp_env); 01114 if (fp_raise_fault(tmp_fp_env)) { 01115 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01116 return; // MACH 01117 } 01118 01119 if (fp_is_nan_or_inf(tmp_default_result)) { 01120 FR[f1] = tmp_default_result; 01121 PR[p2] = 0; 01122 01123 } else { 01124 num = fp_normalize(fp_reg_read(FR[f2])); 01125 den = fp_normalize(fp_reg_read(FR[f3])); 01126 if (fp_is_inf(num) && fp_is_finite(den)) { 01127 FR[f1] = FP_INFINITY; 01128 FR[f1].sign = num.sign ^ den.sign; 01129 PR[p2] = 0; 01130 01131 } else if (fp_is_finite(num) && fp_is_inf(den)) { 01132 FR[f1] = FP_ZERO; 01133 FR[f1].sign = num.sign ^ den.sign; 01134 PR[p2] = 0; 01135 01136 } else if (fp_is_zero(num) && fp_is_finite(den)) { 01137 FR[f1] = FP_ZERO; 01138 FR[f1].sign = num.sign ^ den.sign; 01139 PR[p2] = 0; 01140 01141 } else { 01142 FR[f1] = fp_ieee_recip(den); 01143 PR[p2] = 1; 01144 } 01145 } 01146 fp_update_fpsr(sf, tmp_fp_env); 01147 } 01148 fp_update_psr(f1); 01149 } else { 01150 PR[p2] = 0; 01151 } 01152 /* EAS END */ 01153 }

INLINE void _frsqrta EM_state_type ps,
EM_opcode_sf_type  sf,
EM_uint_t  qp,
EM_uint_t  f1,
EM_uint_t  p2,
EM_uint_t  f3
[static]
 

Definition at line 1277 of file feinstr.c.

References disabled_fp_register_fault, EM_uint_t, fp_check_target_register, fp_decode_fault, fp_exception_fault, fp_ieee_recip_sqrt(), fp_is_nan_or_inf(), fp_is_natval(), fp_is_pos_inf(), fp_is_zero(), fp_normalize(), fp_raise_fault, fp_reg_disabled, fp_reg_read(), fp_update_fpsr, fp_update_psr, FR, frsqrta_exception_fault_check, and PR.

01283 { 01284 EM_uint_t tmp_isrcode; 01285 EM_fp_reg_type tmp_default_result, tmp_fr3; 01286 EM_tmp_fp_env_type tmp_fp_env; 01287 01288 /* EAS START */ 01289 if (PR[qp]) { 01290 fp_check_target_register(f1); 01291 if (tmp_isrcode = fp_reg_disabled(f1, f3, 0, 0)) 01292 disabled_fp_register_fault(tmp_isrcode,0); 01293 01294 if (fp_is_natval(FR[f3])) { 01295 FR[f1] = NATVAL; 01296 PR[p2] = 0; 01297 } else { 01298 tmp_default_result = frsqrta_exception_fault_check(f3, sf, &tmp_fp_env); 01299 if (fp_raise_fault(tmp_fp_env)) { 01300 fp_exception_fault(fp_decode_fault(tmp_fp_env)); 01301 return; // MACH 01302 } 01303 01304 if (fp_is_nan_or_inf(tmp_default_result)) { 01305 FR[f1] = tmp_default_result; 01306 PR[p2] = 0; 01307 } else { 01308 tmp_fr3 = fp_normalize(fp_reg_read(FR[f3])); 01309 if (fp_is_zero(tmp_fr3)) { 01310 FR[f1] = tmp_fr3; 01311 PR[p2] = 0; 01312 } else if (fp_is_pos_inf(tmp_fr3)) { 01313 FR[f1] = tmp_fr3; 01314 PR[p2] = 0; 01315 } else { 01316 FR[f1] = fp_ieee_recip_sqrt(tmp_fr3); 01317 PR[p2] = 1; 01318 } 01319 } 01320 fp_update_fpsr(sf, tmp_fp_env); 01321 } 01322 fp_update_psr(f1); 01323 } else { 01324 PR[p2] = 0; 01325 } 01326 /* EAS END */ 01327 }

void fp82_famax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 323 of file feinstr.c.

References _famax(), EM_uint_t, GETSTATE_F8, and PUTSTATE_F8.

00329 { 00330 GETSTATE_F8(qp,f1,f2,f3); 00331 _famax(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00332 PUTSTATE_F8(f1); 00333 }

void fp82_famin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 307 of file feinstr.c.

References _famin(), EM_uint_t, GETSTATE_F8, and PUTSTATE_F8.

00313 { 00314 GETSTATE_F8(qp,f1,f2,f3); 00315 _famin(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00316 PUTSTATE_F8(f1); 00317 }

void fp82_fcmp_eq EM_state_type ps,
EM_opcode_ctype_type  fctype,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_pred_reg_specifier  p1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 139 of file feinstr.c.

References _fcmp(), EM_uint_t, frelEQ, GETSTATE_F4, and PUTSTATE_F4.

00147 { 00148 GETSTATE_F4(qp,p1,p2,f2,f3); 00149 _fcmp(ps, frelEQ, fctype, sf, (EM_uint_t)qp, 00150 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00151 PUTSTATE_F4(p1,p2); 00152 }

void fp82_fcmp_le EM_state_type ps,
EM_opcode_ctype_type  fctype,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_pred_reg_specifier  p1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 171 of file feinstr.c.

References _fcmp(), EM_uint_t, frelLE, GETSTATE_F4, and PUTSTATE_F4.

00179 { 00180 GETSTATE_F4(qp,p1,p2,f2,f3); 00181 _fcmp(ps, frelLE, fctype, sf, (EM_uint_t)qp, 00182 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00183 PUTSTATE_F4(p1,p2); 00184 }

void fp82_fcmp_lt EM_state_type ps,
EM_opcode_ctype_type  fctype,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_pred_reg_specifier  p1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 155 of file feinstr.c.

References _fcmp(), EM_uint_t, frelLT, GETSTATE_F4, and PUTSTATE_F4.

00163 { 00164 GETSTATE_F4(qp,p1,p2,f2,f3); 00165 _fcmp(ps, frelLT, fctype, sf, (EM_uint_t)qp, 00166 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00167 PUTSTATE_F4(p1,p2); 00168 }

void fp82_fcmp_unord EM_state_type ps,
EM_opcode_ctype_type  fctype,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_pred_reg_specifier  p1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 187 of file feinstr.c.

References _fcmp(), EM_uint_t, frelUNORD, GETSTATE_F4, and PUTSTATE_F4.

00195 { 00196 GETSTATE_F4(qp,p1,p2,f2,f3); 00197 _fcmp(ps, frelUNORD, fctype, sf, (EM_uint_t)qp, 00198 (EM_uint_t)p1, (EM_uint_t)p2, (EM_uint_t)f2, (EM_uint_t)f3); 00199 PUTSTATE_F4(p1,p2); 00200 }

void fp82_fcvt_fx EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 524 of file feinstr.c.

References _fcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, and SIGNED_FORM.

00529 { 00530 GETSTATE_F10(qp,f1,f2); 00531 SIGNED_FORM = 1; 00532 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00533 PUTSTATE_F10(f1); 00534 }

void fp82_fcvt_fx_trunc EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 551 of file feinstr.c.

References _fcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, SIGNED_FORM, and TRUNC_FORM.

00556 { 00557 00558 GETSTATE_F10(qp,f1,f2); 00559 SIGNED_FORM = 1; 00560 TRUNC_FORM = 1; 00561 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00562 PUTSTATE_F10(f1); 00563 }

void fp82_fcvt_fxu EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 537 of file feinstr.c.

References _fcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, and UNSIGNED_FORM.

00542 { 00543 GETSTATE_F10(qp,f1,f2); 00544 UNSIGNED_FORM = 1; 00545 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00546 PUTSTATE_F10(f1); 00547 }

void fp82_fcvt_fxu_trunc EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 567 of file feinstr.c.

References _fcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, TRUNC_FORM, and UNSIGNED_FORM.

00572 { 00573 GETSTATE_F10(qp,f1,f2); 00574 TRUNC_FORM = 1; 00575 UNSIGNED_FORM = 1; 00576 _fcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00577 PUTSTATE_F10(f1); 00578 }

void fp82_fma EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 30 of file feinstr.c.

References _fma(), EM_state_type, GETSTATE_F1, and PUTSTATE_F1.

00038 { 00039 GETSTATE_F1(qp,f1,f3,f4,f2); 00040 _fma(ps, pc, sf, qp, f1, f3, f4, f2); 00041 PUTSTATE_F1(f1); 00042 }

void fp82_fmax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 291 of file feinstr.c.

References _fmax(), GETSTATE_F8, and PUTSTATE_F8.

00297 { 00298 GETSTATE_F8(qp,f1,f2,f3); 00299 _fmax(ps, sf, qp, f1, f2, f3); 00300 PUTSTATE_F8(f1); 00301 }

void fp82_fmin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 275 of file feinstr.c.

References _fmin(), GETSTATE_F8, and PUTSTATE_F8.

00281 { 00282 GETSTATE_F8(qp,f1,f2,f3); 00283 _fmin(ps, sf, qp, f1, f2, f3); 00284 PUTSTATE_F8(f1); 00285 }

void fp82_fms EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 66 of file feinstr.c.

References _fms(), GETSTATE_F1, and PUTSTATE_F1.

00074 { 00075 GETSTATE_F1(qp,f1,f3,f4,f2); 00076 _fms(ps, pc, sf, qp, f1, f3, f4, f2); 00077 PUTSTATE_F1(f1); 00078 }

void fp82_fnma EM_state_type ps,
EM_opcode_pc_type  pc,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 103 of file feinstr.c.

References _fnma(), GETSTATE_F1, and PUTSTATE_F1.

00111 { 00112 GETSTATE_F1(qp,f1,f3,f4,f2); 00113 _fnma(ps, pc, sf, qp, f1, f3, f4, f2); 00114 PUTSTATE_F1(f1); 00115 }

void fp82_fpamax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 390 of file feinstr.c.

References _fpamax(), EM_uint_t, GETSTATE_F8, and PUTSTATE_F8.

00396 { 00397 GETSTATE_F8(qp,f1,f2,f3); 00398 _fpamax(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00399 PUTSTATE_F8(f1); 00400 }

void fp82_fpamin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 373 of file feinstr.c.

References _fpamin(), EM_uint_t, GETSTATE_F8, and PUTSTATE_F8.

00379 { 00380 GETSTATE_F8(qp,f1,f2,f3); 00381 _fpamin(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00382 PUTSTATE_F8(f1); 00383 }

void fp82_fpcmp_eq EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 407 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelEQ, GETSTATE_F8, and PUTSTATE_F8.

00413 { 00414 GETSTATE_F8(qp,f1,f2,f3); 00415 _fpcmp(ps, frelEQ, sf, (EM_uint_t)qp, 00416 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00417 PUTSTATE_F8(f1); 00418 }

void fp82_fpcmp_le EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 436 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelLE, GETSTATE_F8, and PUTSTATE_F8.

00442 { 00443 GETSTATE_F8(qp,f1,f2,f3); 00444 _fpcmp(ps, frelLE, sf, (EM_uint_t)qp, 00445 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00446 PUTSTATE_F8(f1); 00447 }

void fp82_fpcmp_lt EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 422 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelLT, GETSTATE_F8, and PUTSTATE_F8.

00428 { 00429 GETSTATE_F8(qp,f1,f2,f3); 00430 _fpcmp(ps, frelLT, sf, (EM_uint_t)qp, 00431 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00432 PUTSTATE_F8(f1); 00433 }

void fp82_fpcmp_neq EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 464 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelNEQ, GETSTATE_F8, and PUTSTATE_F8.

00470 { 00471 GETSTATE_F8(qp,f1,f2,f3); 00472 _fpcmp(ps, 00473 frelNEQ, sf, (EM_uint_t)qp, 00474 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00475 PUTSTATE_F8(f1); 00476 }

void fp82_fpcmp_nle EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 493 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelNLE, GETSTATE_F8, and PUTSTATE_F8.

00499 { 00500 GETSTATE_F8(qp,f1,f2,f3); 00501 _fpcmp(ps, frelNLE, sf, (EM_uint_t)qp, 00502 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00503 PUTSTATE_F8(f1); 00504 }

void fp82_fpcmp_nlt EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 479 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelNLT, GETSTATE_F8, and PUTSTATE_F8.

00485 { 00486 GETSTATE_F8(qp,f1,f2,f3); 00487 _fpcmp(ps, frelNLT, sf, (EM_uint_t)qp, 00488 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00489 PUTSTATE_F8(f1); 00490 }

void fp82_fpcmp_ord EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 507 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelORD, GETSTATE_F8, and PUTSTATE_F8.

00513 { 00514 GETSTATE_F8(qp,f1,f2,f3); 00515 _fpcmp(ps, frelORD, sf, (EM_uint_t)qp, 00516 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00517 PUTSTATE_F8(f1); 00518 }

void fp82_fpcmp_unord EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 450 of file feinstr.c.

References _fpcmp(), EM_uint_t, frelUNORD, GETSTATE_F8, and PUTSTATE_F8.

00456 { 00457 GETSTATE_F8(qp,f1,f2,f3); 00458 _fpcmp(ps, frelUNORD, sf, (EM_uint_t)qp, 00459 (EM_uint_t)f1, (EM_uint_t)f2, (EM_uint_t)f3); 00460 PUTSTATE_F8(f1); 00461 }

void fp82_fpcvt_fx EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 585 of file feinstr.c.

References _fpcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, and SIGNED_FORM.

00590 { 00591 GETSTATE_F10(qp,f1,f2); 00592 SIGNED_FORM = 1; 00593 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00594 PUTSTATE_F10(f1); 00595 }

void fp82_fpcvt_fx_trunc EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 612 of file feinstr.c.

References _fpcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, SIGNED_FORM, and TRUNC_FORM.

00617 { 00618 00619 GETSTATE_F10(qp,f1,f2); 00620 SIGNED_FORM = 1; 00621 TRUNC_FORM = 1; 00622 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00623 PUTSTATE_F10(f1); 00624 }

void fp82_fpcvt_fxu EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 599 of file feinstr.c.

References _fpcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, and UNSIGNED_FORM.

00604 { 00605 GETSTATE_F10(qp,f1,f2); 00606 UNSIGNED_FORM = 1; 00607 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00608 PUTSTATE_F10(f1); 00609 }

void fp82_fpcvt_fxu_trunc EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2
 

Definition at line 627 of file feinstr.c.

References _fpcvt_fx(), EM_uint_t, GETSTATE_F10, PUTSTATE_F10, TRUNC_FORM, and UNSIGNED_FORM.

00632 { 00633 GETSTATE_F10(qp,f1,f2); 00634 TRUNC_FORM = 1; 00635 UNSIGNED_FORM = 1; 00636 _fpcvt_fx(ps, sf, (EM_uint_t)qp, (EM_uint_t)f1, (EM_uint_t)f2); 00637 PUTSTATE_F10(f1); 00638 }

void fp82_fpma EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 49 of file feinstr.c.

References _fpma(), GETSTATE_F1, and PUTSTATE_F1.

00056 { 00057 GETSTATE_F1(qp,f1,f3,f4,f2); 00058 _fpma(ps, sf, qp, f1, f3, f4, f2); 00059 PUTSTATE_F1(f1); 00060 }

void fp82_fpmax EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 357 of file feinstr.c.

References _fpmax(), GETSTATE_F8, and PUTSTATE_F8.

00363 { 00364 GETSTATE_F8(qp,f1,f2,f3); 00365 _fpmax(ps, sf, qp, f1, f2, f3); 00366 PUTSTATE_F8(f1); 00367 }

void fp82_fpmin EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 340 of file feinstr.c.

References _fpmin(), GETSTATE_F8, and PUTSTATE_F8.

00346 { 00347 GETSTATE_F8(qp,f1,f2,f3); 00348 _fpmin(ps, sf, qp, f1, f2, f3); 00349 PUTSTATE_F8(f1); 00350 }

void fp82_fpms EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 85 of file feinstr.c.

References _fpms(), GETSTATE_F1, and PUTSTATE_F1.

00092 { 00093 GETSTATE_F1(qp,f1,f3,f4,f2); 00094 _fpms(ps, sf, qp, f1, f3, f4, f2); 00095 PUTSTATE_F1(f1); 00096 }

void fp82_fpnma EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_fp_reg_specifier  f3,
EM_fp_reg_specifier  f4,
EM_fp_reg_specifier  f2
 

Definition at line 121 of file feinstr.c.

References _fpnma(), GETSTATE_F1, and PUTSTATE_F1.

00128 { 00129 GETSTATE_F1(qp,f1,f3,f4,f2); 00130 _fpnma(ps, sf, qp, f1, f3, f4, f2); 00131 PUTSTATE_F1(f1); 00132 }

void fp82_fprcpa EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 224 of file feinstr.c.

References _fprcpa(), GETSTATE_F6, and PUTSTATE_F6.

00231 { 00232 GETSTATE_F6(qp,f1,p2,f2,f3); 00233 _fprcpa(ps, sf, qp, f1, p2, f2, f3); 00234 PUTSTATE_F6(f1,p2); 00235 }

void fp82_fprsqrta EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f3
 

Definition at line 259 of file feinstr.c.

References _fprsqrta(), GETSTATE_F7, and PUTSTATE_F7.

00265 { 00266 GETSTATE_F7(qp,f1,p2,f3); 00267 _fprsqrta(ps, sf, qp, f1, p2, f3); 00268 PUTSTATE_F7(f1,p2); 00269 }

void fp82_frcpa EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f2,
EM_fp_reg_specifier  f3
 

Definition at line 207 of file feinstr.c.

References _frcpa(), GETSTATE_F6, and PUTSTATE_F6.

00214 { 00215 GETSTATE_F6(qp,f1,p2,f2,f3); 00216 _frcpa(ps, sf, qp, f1, p2, f2, f3); 00217 PUTSTATE_F6(f1,p2); 00218 }

void fp82_frsqrta EM_state_type ps,
EM_opcode_sf_type  sf,
EM_pred_reg_specifier  qp,
EM_fp_reg_specifier  f1,
EM_pred_reg_specifier  p2,
EM_fp_reg_specifier  f3
 

Definition at line 243 of file feinstr.c.

References _frsqrta(), GETSTATE_F7, and PUTSTATE_F7.

00249 { 00250 GETSTATE_F7(qp,f1,p2,f3); 00251 _frsqrta(ps, sf, qp, f1, p2, f3); 00252 PUTSTATE_F7(f1,p2); 00253 }

EM_fp_reg_type fp_ieee_recip EM_fp_reg_type  den  )  [static]
 

Definition at line 2036 of file feinstr.c.

References EM_int_t, EM_uint64_t, EM_uint_t, fp_reg_struct::exponent, fp_extract_bits(), fp_reg_struct::sign, and fp_reg_struct::significand.

02038 { 02039 EM_uint_t tmp_index; 02040 EM_fp_reg_type tmp_res; 02041 02042 /* EAS START */ 02043 const EM_uint_t RECIP_TABLE[256] = { 02044 0x3fc, 0x3f4, 0x3ec, 0x3e4, 0x3dd, 0x3d5, 0x3cd, 0x3c6, 02045 0x3be, 0x3b7, 0x3af, 0x3a8, 0x3a1, 0x399, 0x392, 0x38b, 02046 0x384, 0x37d, 0x376, 0x36f, 0x368, 0x361, 0x35b, 0x354, 02047 0x34d, 0x346, 0x340, 0x339, 0x333, 0x32c, 0x326, 0x320, 02048 0x319, 0x313, 0x30d, 0x307, 0x300, 0x2fa, 0x2f4, 0x2ee, 02049 0x2e8, 0x2e2, 0x2dc, 0x2d7, 0x2d1, 0x2cb, 0x2c5, 0x2bf, 02050 0x2ba, 0x2b4, 0x2af, 0x2a9, 0x2a3, 0x29e, 0x299, 0x293, 02051 0x28e, 0x288, 0x283, 0x27e, 0x279, 0x273, 0x26e, 0x269, 02052 0x264, 0x25f, 0x25a, 0x255, 0x250, 0x24b, 0x246, 0x241, 02053 0x23c, 0x237, 0x232, 0x22e, 0x229, 0x224, 0x21f, 0x21b, 02054 0x216, 0x211, 0x20d, 0x208, 0x204, 0x1ff, 0x1fb, 0x1f6, 02055 0x1f2, 0x1ed, 0x1e9, 0x1e5, 0x1e0, 0x1dc, 0x1d8, 0x1d4, 02056 0x1cf, 0x1cb, 0x1c7, 0x1c3, 0x1bf, 0x1bb, 0x1b6, 0x1b2, 02057 0x1ae, 0x1aa, 0x1a6, 0x1a2, 0x19e, 0x19a, 0x197, 0x193, 02058 0x18f, 0x18b, 0x187, 0x183, 0x17f, 0x17c, 0x178, 0x174, 02059 0x171, 0x16d, 0x169, 0x166, 0x162, 0x15e, 0x15b, 0x157, 02060 0x154, 0x150, 0x14d, 0x149, 0x146, 0x142, 0x13f, 0x13b, 02061 0x138, 0x134, 0x131, 0x12e, 0x12a, 0x127, 0x124, 0x120, 02062 0x11d, 0x11a, 0x117, 0x113, 0x110, 0x10d, 0x10a, 0x107, 02063 0x103, 0x100, 0x0fd, 0x0fa, 0x0f7, 0x0f4, 0x0f1, 0x0ee, 02064 0x0eb, 0x0e8, 0x0e5, 0x0e2, 0x0df, 0x0dc, 0x0d9, 0x0d6, 02065 0x0d3, 0x0d0, 0x0cd, 0x0ca, 0x0c8, 0x0c5, 0x0c2, 0x0bf, 02066 0x0bc, 0x0b9, 0x0b7, 0x0b4, 0x0b1, 0x0ae, 0x0ac, 0x0a9, 02067 0x0a6, 0x0a4, 0x0a1, 0x09e, 0x09c, 0x099, 0x096, 0x094, 02068 0x091, 0x08e, 0x08c, 0x089, 0x087, 0x084, 0x082, 0x07f, 02069 0x07c, 0x07a, 0x077, 0x075, 0x073, 0x070, 0x06e, 0x06b, 02070 0x069, 0x066, 0x064, 0x061, 0x05f, 0x05d, 0x05a, 0x058, 02071 0x056, 0x053, 0x051, 0x04f, 0x04c, 0x04a, 0x048, 0x045, 02072 0x043, 0x041, 0x03f, 0x03c, 0x03a, 0x038, 0x036, 0x033, 02073 0x031, 0x02f, 0x02d, 0x02b, 0x029, 0x026, 0x024, 0x022, 02074 0x020, 0x01e, 0x01c, 0x01a, 0x018, 0x015, 0x013, 0x011, 02075 0x00f, 0x00d, 0x00b, 0x009, 0x007, 0x005, 0x003, 0x001, 02076 }; 02077 02078 02079 tmp_index = fp_extract_bits(den.significand,62,55); 02080 tmp_res.significand = ((EM_uint64_t)1 << 63) | ((EM_uint64_t)RECIP_TABLE[tmp_index] << 53); 02081 tmp_res.exponent = (EM_int_t)FP_REG_EXP_ONES - 2 - (EM_int_t)den.exponent; 02082 tmp_res.sign = den.sign; 02083 return (tmp_res); 02084 02085 /* EAS END */ 02086 }

EM_fp_reg_type fp_ieee_recip_sqrt EM_fp_reg_type  root  )  [static]
 

Definition at line 2092 of file feinstr.c.

References EM_int_t, EM_uint64_t, EM_uint_t, fp_reg_struct::exponent, fp_extract_bits(), fp_reg_struct::sign, and fp_reg_struct::significand.

02094 { 02095 EM_uint_t tmp_index; 02096 EM_fp_reg_type tmp_res; 02097 02098 /* EAS START */ 02099 const EM_uint_t RECIP_SQRT_TABLE[256] = { 02100 0x1a5, 0x1a0, 0x19a, 0x195, 0x18f, 0x18a, 0x185, 0x180, 02101 0x17a, 0x175, 0x170, 0x16b, 0x166, 0x161, 0x15d, 0x158, 02102 0x153, 0x14e, 0x14a, 0x145, 0x140, 0x13c, 0x138, 0x133, 02103 0x12f, 0x12a, 0x126, 0x122, 0x11e, 0x11a, 0x115, 0x111, 02104 0x10d, 0x109, 0x105, 0x101, 0x0fd, 0x0fa, 0x0f6, 0x0f2, 02105 0x0ee, 0x0ea, 0x0e7, 0x0e3, 0x0df, 0x0dc, 0x0d8, 0x0d5, 02106 0x0d1, 0x0ce, 0x0ca, 0x0c7, 0x0c3, 0x0c0, 0x0bd, 0x0b9, 02107 0x0b6, 0x0b3, 0x0b0, 0x0ad, 0x0a9, 0x0a6, 0x0a3, 0x0a0, 02108 0x09d, 0x09a, 0x097, 0x094, 0x091, 0x08e, 0x08b, 0x088, 02109 0x085, 0x082, 0x07f, 0x07d, 0x07a, 0x077, 0x074, 0x071, 02110 0x06f, 0x06c, 0x069, 0x067, 0x064, 0x061, 0x05f, 0x05c, 02111 0x05a, 0x057, 0x054, 0x052, 0x04f, 0x04d, 0x04a, 0x048, 02112 0x045, 0x043, 0x041, 0x03e, 0x03c, 0x03a, 0x037, 0x035, 02113 0x033, 0x030, 0x02e, 0x02c, 0x029, 0x027, 0x025, 0x023, 02114 0x020, 0x01e, 0x01c, 0x01a, 0x018, 0x016, 0x014, 0x011, 02115 0x00f, 0x00d, 0x00b, 0x009, 0x007, 0x005, 0x003, 0x001, 02116 0x3fc, 0x3f4, 0x3ec, 0x3e5, 0x3dd, 0x3d5, 0x3ce, 0x3c7, 02117 0x3bf, 0x3b8, 0x3b1, 0x3aa, 0x3a3, 0x39c, 0x395, 0x38e, 02118 0x388, 0x381, 0x37a, 0x374, 0x36d, 0x367, 0x361, 0x35a, 02119 0x354, 0x34e, 0x348, 0x342, 0x33c, 0x336, 0x330, 0x32b, 02120 0x325, 0x31f, 0x31a, 0x314, 0x30f, 0x309, 0x304, 0x2fe, 02121 0x2f9, 0x2f4, 0x2ee, 0x2e9, 0x2e4, 0x2df, 0x2da, 0x2d5, 02122 0x2d0, 0x2cb, 0x2c6, 0x2c1, 0x2bd, 0x2b8, 0x2b3, 0x2ae, 02123 0x2aa, 0x2a5, 0x2a1, 0x29c, 0x298, 0x293, 0x28f, 0x28a, 02124 0x286, 0x282, 0x27d, 0x279, 0x275, 0x271, 0x26d, 0x268, 02125 0x264, 0x260, 0x25c, 0x258, 0x254, 0x250, 0x24c, 0x249, 02126 0x245, 0x241, 0x23d, 0x239, 0x235, 0x232, 0x22e, 0x22a, 02127 0x227, 0x223, 0x220, 0x21c, 0x218, 0x215, 0x211, 0x20e, 02128 0x20a, 0x207, 0x204, 0x200, 0x1fd, 0x1f9, 0x1f6, 0x1f3, 02129 0x1f0, 0x1ec, 0x1e9, 0x1e6, 0x1e3, 0x1df, 0x1dc, 0x1d9, 02130 0x1d6, 0x1d3, 0x1d0, 0x1cd, 0x1ca, 0x1c7, 0x1c4, 0x1c1, 02131 0x1be, 0x1bb, 0x1b8, 0x1b5, 0x1b2, 0x1af, 0x1ac, 0x1aa, 02132 }; 02133 02134 tmp_index = (fp_extract_bits((EM_uint64_t)root.exponent,0,0) << 7) | 02135 fp_extract_bits(root.significand,62,56); 02136 02137 tmp_res.significand = ((EM_uint64_t)1 << 63) |((EM_uint64_t)RECIP_SQRT_TABLE[tmp_index] << 53); 02138 tmp_res.exponent = ((EM_int_t)FP_REG_EXP_HALF) - ((((EM_int_t)root.exponent) - ((EM_int_t)FP_REG_BIAS)) >> 1); 02139 tmp_res.sign = FP_SIGN_POSITIVE; 02140 return(tmp_res); 02141 02142 /* EAS END */ 02143 }


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