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#include "ki.h"
00007
00008
#ifndef WIN32_OR_WIN64
00009
#include <stdlib.h>
00010
#include <stdio.h>
00011
#include <memory.h>
00012
#endif
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00014
#include "fepublic.h"
00015
#include "fehelper.h"
00016
#include "festate.h"
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00019
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00021
00022
00023
00024
00025
00026
00027
00028
EM_uint64_t
00029 fp_concatenate(
EM_uint_t hi_val, EM_uint_t lo_val) {
00030
return( ((
EM_uint64_t)hi_val <<32)
00031 | ((
EM_uint64_t)lo_val &
CONST_FORMAT(0x00000000FFFFFFFF )) );
00032 }
00033
00034
00035
EM_uint_t
00036 fp_extract_bits(
00037 EM_uint64_t input_value,
00038
unsigned int hi_bound,
00039
unsigned int lo_bound)
00040 {
00041
EM_uint64_t value;
00042
if(lo_bound >63)
return(0x00000000);
00043
00044 value = (input_value >> lo_bound) &
00045 ~(
CONST_FORMAT(0xFFFFFFFFFFFFFFFF) << (hi_bound - lo_bound + 1));
00046
00047
return((
EM_uint_t)value);
00048 }
00049
00050
00051
INLINE EM_fp_reg_type
00052 fp_reg_read_hi(EM_uint_t freg)
00053 {
00054
EM_fp_reg_type tmp_freg =
FR[freg];
00055
EM_memory_type mem;
00056
00057
if (freg == 0)
00058
return (FP_ZERO);
00059
else if (freg == 1) {
00060
return (FP_NEG_ZERO);
00061 }
00062
else {
00063 mem.
uint_32.
uvalue = (
EM_uint_t)(tmp_freg.
significand >> 32);
00064 tmp_freg =
fp_mem_to_fr_format(mem, 4, 0);
00065
return (tmp_freg);
00066 }
00067 }
00068
00069
INLINE EM_fp_reg_type
00070 fp_reg_read_lo(EM_uint_t freg)
00071 {
00072
EM_fp_reg_type tmp_freg =
FR[freg];
00073
EM_memory_type mem;
00074
EM_uint64_t tmp_val;
00075
EM_uint_t tmp32_val;
00076
00077
if (freg == 0)
00078
return (FP_ZERO);
00079
else if (freg == 1) {
00080
return (FP_ZERO);
00081 }
00082
else {
00083 tmp_val = (tmp_freg.
significand &
CONST_FORMAT(0x00000000ffffffff));
00084 tmp32_val = (
EM_uint_t)tmp_val;
00085 mem.
uint_32.
uvalue = tmp32_val;
00086 tmp_freg =
fp_mem_to_fr_format(mem, 4, 0);
00087
return (tmp_freg);
00088 }
00089 }
00090
00091
00092
#undef fp_reg_read_hi
00093
#undef fp_reg_read_lo
00094
00095 #define fp_reg_read_hi(f2) fp82_reg_read_hi(ps,f2)
00096 #define fp_reg_read_lo(f3) fp82_reg_read_lo(ps,f3)
00097
00098
00099
00100
00101
00102
EM_memory_type
00103 fp_fr_to_mem_format(
00104
EM_fp_reg_type freg,
00105 EM_uint_t size,
00106 EM_uint_t integer_form)
00107 {
00108
EM_memory_type tmp_mem;
00109
EM_uint64_t tmp_significand;
00110
00111
switch(size) {
00112
case 4:
00113 tmp_mem.
fp_single.
sign = freg.
sign;
00114
if (freg.
exponent == 0)
00115 tmp_mem.
fp_single.
exponent = 0;
00116
else if ((freg.
significand>>63) == 0)
00117 tmp_mem.
fp_single.
exponent = 0;
00118
else if (freg.
exponent == FP_REG_EXP_ONES)
00119 tmp_mem.
fp_single.
exponent = FP_SGL_EXP_ONES;
00120
else
00121 tmp_mem.
fp_single.
exponent =
00122 ((freg.
exponent
00123 >> (FP_REG_EXP_WIDTH-1) & 1)
00124 << (FP_SGL_EXP_WIDTH-1))
00125 |( freg.
exponent & FP_SGL_BIAS);
00126
00127 tmp_mem.
fp_single.
significand =
00128 (
EM_uint_t)((freg.
significand <<1) >>(63-22));
00129
break;
00130
00131
case 8:
00132
if (integer_form)
00133 tmp_mem.
uint_64.
uvalue = freg.
significand;
00134
00135
else {
00136 tmp_mem.
fp_double.
sign = freg.
sign;
00137
if (freg.
exponent == 0)
00138 tmp_mem.
fp_double.
exponent = 0;
00139
else if ((freg.
significand>>63) == 0)
00140 tmp_mem.
fp_double.
exponent = 0;
00141
else if (freg.
exponent == FP_REG_EXP_ONES)
00142 tmp_mem.
fp_double.
exponent = FP_DBL_EXP_ONES;
00143
else
00144 tmp_mem.
fp_double.
exponent =
00145 ((freg.
exponent
00146 >> (FP_REG_EXP_WIDTH-1) & 1)
00147 << (FP_DBL_EXP_WIDTH-1))
00148 |( freg.
exponent & FP_DBL_BIAS);
00149
00150 tmp_significand =
00151 (freg.
significand <<1) >> (63-51);
00152
00153 tmp_mem.
fp_double.
significand_hi =
00154 (
EM_uint_t)((tmp_significand >> 32) &
CONST_FORMAT( 0x00000000ffffffff));
00155 tmp_mem.
fp_double.
significand_lo =
00156 (
EM_uint_t)(tmp_significand &
CONST_FORMAT( 0x00000000ffffffff));
00157 }
00158
break;
00159
00160
case 10:
00161 tmp_mem.
fp_double_extended.
sign = freg.
sign;
00162
if (freg.
exponent == 0) {
00163
00164 tmp_mem.
fp_double_extended.
exponent = 0;
00165 }
else if (freg.
exponent == FP_REG_EXP_ONES) {
00166
00167 tmp_mem.
fp_double_extended.
exponent = FP_EXT_EXP_ONES;
00168 }
else {
00169
00170 tmp_mem.
fp_double_extended.
exponent =
00171 ((freg.
exponent
00172 >> (FP_REG_EXP_WIDTH-1) & 1)
00173 << (FP_EXT_EXP_WIDTH-1))
00174 |( freg.
exponent & FP_EXT_BIAS);
00175
00176 }
00177 memcpy(tmp_mem.
fp_double_extended.
significand,
00178 &freg.
significand, 8);
00179
00180
break;
00181
00182
case 16:
00183 tmp_mem.
fp_spill_fill.
reserved1 = 0;
00184 tmp_mem.
fp_spill_fill.
reserved2 = 0;
00185 tmp_mem.
fp_spill_fill.
sign = freg.
sign;
00186 tmp_mem.
fp_spill_fill.
exponent = freg.
exponent;
00187 tmp_mem.
fp_spill_fill.
significand = freg.
significand;
00188
break;
00189 }
00190
return (tmp_mem);
00191 }
00192
00193
00194
INLINE EM_memory_type
00195 fr_to_mem4_bias_adjust(
EM_fp_reg_type freg)
00196 {
00197
EM_memory_type tmp_mem;
00198
00199 tmp_mem.
fp_single.
sign = freg.
sign;
00200
if (freg.
exponent == 0)
00201 tmp_mem.
fp_single.
exponent = 0;
00202
else if (freg.
exponent == FP_REG_EXP_ONES)
00203 tmp_mem.
fp_single.
exponent = FP_SGL_EXP_ONES;
00204
else if ((freg.
significand>>63) == 0)
00205 tmp_mem.
fp_single.
exponent = (
EM_uint_t)
00206 (((
EM_int_t)freg.
exponent)
00207 - FP_REG_BIAS + FP_SGL_BIAS - 1);
00208
else
00209 tmp_mem.
fp_single.
exponent = (
EM_uint_t)
00210 (((
EM_int_t)freg.
exponent)
00211 - FP_REG_BIAS + FP_SGL_BIAS);
00212 tmp_mem.
fp_single.
significand = (
EM_uint_t) (
00213 (freg.
significand<<(64-62-1))>>(40+64-62-1));
00214
00215
return (tmp_mem);
00216 }
00217
00218
00219
00220
00221
00222
00223
00224
00225
INLINE EM_boolean_t
00226 fp_equal(
EM_fp_reg_type fr1,
EM_fp_reg_type fr2)
00227 {
00228
EM_fp_dp_type fp_dp1;
00229
EM_fp_dp_type fp_dp2;
00230
00231
if (
fp_is_nan(fr1) ||
fp_is_nan(fr2)
00232 ||
fp_is_unsupported(fr1) ||
fp_is_unsupported(fr2) )
00233
return (0);
00234
00235 fp_dp1 =
fp_fr_to_dp(fr1);
00236 fp_dp2 =
fp_fr_to_dp(fr2);
00237
00238
if ( (fp_dp1.
sign == fp_dp2.
sign )
00239 && (fp_dp1.
exponent == fp_dp2.
exponent )
00240 && (fp_dp1.
significand.
hi == fp_dp2.
significand.
hi)
00241 && (fp_dp1.
significand.
lo == fp_dp2.
significand.
lo) )
00242
return (1);
00243
else if (
fp_is_zero_dp(fp_dp1) &&
fp_is_zero_dp(fp_dp2) )
00244
return (1);
00245
else
00246
return (0);
00247 }
00248
00249
00250
INLINE EM_boolean_t
00251 fp_less_than(
00252
EM_fp_reg_type fr1,
00253
EM_fp_reg_type fr2)
00254 {
00255
EM_fp_dp_type fp_dp1;
00256
EM_fp_dp_type fp_dp2;
00257
00258
if (
fp_is_nan(fr1) ||
fp_is_nan(fr2)
00259 ||
fp_is_unsupported(fr1) ||
fp_is_unsupported(fr2) )
00260
return (0);
00261
00262 fp_dp1 =
fp_fr_to_dp(fr1);
00263 fp_dp2 =
fp_fr_to_dp(fr2);
00264
00265
if (
fp_is_neg_dp(fp_dp1) &&
fp_is_pos_dp(fp_dp2)) {
00266
if (!
fp_is_zero_dp(fp_dp1) || !
fp_is_zero_dp(fp_dp2) )
00267
return (1);
00268
else
00269
return (0);
00270 }
else if (
fp_is_pos_dp(fp_dp1) &&
fp_is_neg_dp(fp_dp2)) {
00271
return (0);
00272 }
else if (
fp_is_neg_dp(fp_dp1) &&
fp_is_neg_dp(fp_dp2)) {
00273
if (fp_dp1.
exponent > fp_dp2.
exponent)
00274
return (1);
00275
else if ((fp_dp1.
exponent == fp_dp2.
exponent)
00276 && (
fp_U128_gt(fp_dp1.
significand, fp_dp2.
significand)))
00277
return (1);
00278
else
00279
return (0);
00280 }
else if (
fp_is_pos_dp(fp_dp1) &&
fp_is_pos_dp(fp_dp2)) {
00281
if (fp_dp1.
exponent < fp_dp2.
exponent)
00282
return (1);
00283
else if ((fp_dp1.
exponent == fp_dp2.
exponent)
00284 && (
fp_U128_lt(fp_dp1.
significand, fp_dp2.
significand)))
00285
return (1);
00286
else
00287
return (0);
00288 }
else {
00289
return (0);
00290 }
00291 }
00292
00293
INLINE EM_boolean_t
00294 fp_lesser_or_equal(
EM_fp_reg_type fr1,
EM_fp_reg_type fr2)
00295 {
00296
EM_fp_dp_type fp_dp1;
00297
EM_fp_dp_type fp_dp2;
00298
00299
if (
fp_is_nan(fr1) ||
fp_is_nan(fr2)
00300 ||
fp_is_unsupported(fr1) ||
fp_is_unsupported(fr2) )
00301
return (0);
00302
00303 fp_dp1 =
fp_fr_to_dp(fr1);
00304 fp_dp2 =
fp_fr_to_dp(fr2);
00305
00306
if (
fp_is_neg_dp(fp_dp1) &&
fp_is_pos_dp(fp_dp2)) {
00307
return (1);
00308 }
else if (
fp_is_pos_dp(fp_dp1) &&
fp_is_neg_dp(fp_dp2)) {
00309
if (
fp_is_zero_dp(fp_dp1) &&
fp_is_zero_dp(fp_dp2))
00310
return (1);
00311
else
00312
return (0);
00313 }
else if (
fp_is_neg_dp(fp_dp1) &&
fp_is_neg_dp(fp_dp2)) {
00314
if (fp_dp1.
exponent > fp_dp2.
exponent)
00315
return (1);
00316
else if ((fp_dp1.
exponent == fp_dp2.
exponent)
00317 && (
fp_U128_ge(fp_dp1.
significand, fp_dp2.
significand)))
00318
return (1);
00319
else
00320
return (0);
00321 }
else if (
fp_is_pos_dp(fp_dp1) &&
fp_is_pos_dp(fp_dp2)) {
00322
if (fp_dp1.
exponent < fp_dp2.
exponent)
00323
return (1);
00324
else if ((fp_dp1.
exponent == fp_dp2.
exponent)
00325 && (
fp_U128_le(fp_dp1.
significand, fp_dp2.
significand)))
00326
return (1);
00327
else
00328
return (0);
00329 }
else {
00330
return (0);
00331 }
00332 }
00333
00334
INLINE EM_boolean_t
00335 fp_unordered(
EM_fp_reg_type fr1,
EM_fp_reg_type fr2)
00336 {
00337
if (
fp_is_nan(fr1) ||
fp_is_nan(fr2)
00338 ||
fp_is_unsupported(fr1) ||
fp_is_unsupported(fr2) )
00339
return (1);
00340
else
00341
return (0);
00342
00343 }
00344
00345
EM_uint_t
00346 fp82_fp_decode_fault(
EM_tmp_fp_env_type tmp_fp_env)
00347 {
00348
EM_uint_t tmp_ret = 0;
00349
00350
if (!tmp_fp_env.
simd) {
00351
00352
if (tmp_fp_env.
em_faults.
swa)
00353
return (8);
00354
else if (tmp_fp_env.
em_faults.
v)
00355
return (1);
00356
else if (tmp_fp_env.
em_faults.
z)
00357
return (4);
00358
else if (tmp_fp_env.
em_faults.
d)
00359
return (2);
00360
else {
00361 tmp_ret = 0;
00362
return (0);
00363 }
00364
00365 }
else {
00366
00367
00368
00369
00370
00371
00372
if (tmp_fp_env.
hi_faults.
swa)
00373 tmp_ret = 8;
00374
else if (tmp_fp_env.
hi_faults.
v)
00375 tmp_ret = 1;
00376
else if (tmp_fp_env.
hi_faults.
z)
00377 tmp_ret = 4;
00378
else if (tmp_fp_env.
hi_faults.
d)
00379 tmp_ret = 2;
00380
00381
if (tmp_fp_env.
lo_faults.
swa)
00382 tmp_ret |= 8<<4;
00383
else if (tmp_fp_env.
lo_faults.
v)
00384 tmp_ret |= 1<<4;
00385
else if (tmp_fp_env.
lo_faults.
z)
00386 tmp_ret |= 4<<4;
00387
else if (tmp_fp_env.
lo_faults.
d)
00388 tmp_ret |= 2<<4;
00389
return (tmp_ret);
00390 }
00391 }
00392
00393
00394
EM_uint_t
00395 fp82_fp_decode_trap(
EM_tmp_fp_env_type tmp_fp_env)
00396 {
00397
EM_uint_t tmp_ret;
00398
00399
if (!tmp_fp_env.
simd) {
00400 tmp_ret = (tmp_fp_env.
ebc <<15
00401 | tmp_fp_env.
fpa <<14
00402 | tmp_fp_env.
em_traps.
i<<13
00403 | tmp_fp_env.
em_traps.
un<<12
00404 | tmp_fp_env.
em_traps.
o<<11 );
00405 }
00406
else {
00407 tmp_ret = 0;
00408
if(tmp_fp_env.
hi_traps.
i ||
00409 tmp_fp_env.
hi_traps.
un ||
00410 tmp_fp_env.
hi_traps.
o ) {
00411
00412 tmp_ret = tmp_fp_env.
hi_fpa <<14
00413 | tmp_fp_env.
hi_traps.
i<<13
00414 | tmp_fp_env.
hi_flags.
i<<13
00415 | tmp_fp_env.
hi_traps.
un<<12
00416 | tmp_fp_env.
hi_traps.
o<<11;
00417 }
00418
00419
if(tmp_fp_env.
lo_traps.
i ||
00420 tmp_fp_env.
lo_traps.
un ||
00421 tmp_fp_env.
lo_traps.
o ) {
00422
00423 tmp_ret |= tmp_fp_env.
lo_fpa <<10
00424 | tmp_fp_env.
lo_traps.
i<<9
00425 | tmp_fp_env.
lo_flags.
i<<9
00426 | tmp_fp_env.
lo_traps.
un<<8
00427 | tmp_fp_env.
lo_traps.
o<<7;
00428 }
00429 }
00430
return (tmp_ret);
00431 }
00432
00433
00434
void
00435 fp_decode_environment(
00436 EM_opcode_pc_type pc,
00437 EM_opcode_sf_type sf,
00438
EM_tmp_fp_env_type *tmp_fp_env)
00439 {
00440
EM_sf_type tmp_sf;
00441
00442
if (sf ==
sfS0) {
00443 tmp_sf.
controls.
ftz =
FPSR.sf0_controls_ftz;
00444 tmp_sf.
controls.
wre =
FPSR.sf0_controls_wre;
00445 tmp_sf.
controls.
pc =
FPSR.sf0_controls_pc;
00446 tmp_sf.
controls.
rc =
FPSR.sf0_controls_rc;
00447 tmp_sf.
controls.
td =
FPSR.sf0_controls_td;
00448 }
else if (sf ==
sfS1) {
00449 tmp_sf.
controls.
ftz =
FPSR.sf1_controls_ftz;
00450 tmp_sf.
controls.
wre =
FPSR.sf1_controls_wre;
00451 tmp_sf.
controls.
pc =
FPSR.sf1_controls_pc;
00452 tmp_sf.
controls.
rc =
FPSR.sf1_controls_rc;
00453 tmp_sf.
controls.
td =
FPSR.sf1_controls_td;
00454 }
else if (sf ==
sfS2) {
00455 tmp_sf.
controls.
ftz =
FPSR.sf2_controls_ftz;
00456 tmp_sf.
controls.
wre =
FPSR.sf2_controls_wre;
00457 tmp_sf.
controls.
pc =
FPSR.sf2_controls_pc;
00458 tmp_sf.
controls.
rc =
FPSR.sf2_controls_rc;
00459 tmp_sf.
controls.
td =
FPSR.sf2_controls_td;
00460 }
else if (sf ==
sfS3) {
00461 tmp_sf.
controls.
ftz =
FPSR.sf3_controls_ftz;
00462 tmp_sf.
controls.
wre =
FPSR.sf3_controls_wre;
00463 tmp_sf.
controls.
pc =
FPSR.sf3_controls_pc;
00464 tmp_sf.
controls.
rc =
FPSR.sf3_controls_rc;
00465 tmp_sf.
controls.
td =
FPSR.sf3_controls_td;
00466 }
else {
00467 tmp_sf.
controls.
ftz = 0;
00468 tmp_sf.
controls.
wre = 1;
00469 tmp_sf.
controls.
pc =
sf_double_extended;
00470 tmp_sf.
controls.
rc =
rc_rn;
00471 tmp_sf.
controls.
td = 1;
00472 }
00473
00474
if (sf ==
sf_none) {
00475 tmp_fp_env->
controls.
vd = 0;
00476 tmp_fp_env->
controls.
dd = 0;
00477 tmp_fp_env->
controls.
zd = 0;
00478 tmp_fp_env->
controls.
od = 0;
00479 tmp_fp_env->
controls.
ud = 0;
00480 tmp_fp_env->
controls.
id = 0;
00481
00482 }
else if (tmp_sf.
controls.
td ) {
00483 tmp_fp_env->
controls.
vd = 1;
00484 tmp_fp_env->
controls.
dd = 1;
00485 tmp_fp_env->
controls.
zd = 1;
00486 tmp_fp_env->
controls.
od = 1;
00487 tmp_fp_env->
controls.
ud = 1;
00488 tmp_fp_env->
controls.
id = 1;
00489
00490 }
else {
00491 tmp_fp_env->
controls.
vd =
FPSR.traps_vd;
00492 tmp_fp_env->
controls.
dd =
FPSR.traps_dd;
00493 tmp_fp_env->
controls.
zd =
FPSR.traps_zd;
00494 tmp_fp_env->
controls.
od =
FPSR.traps_od;
00495 tmp_fp_env->
controls.
ud =
FPSR.traps_ud;
00496 tmp_fp_env->
controls.
id =
FPSR.traps_id;
00497 }
00498
00499
if (pc ==
pc_none) {
00500 tmp_fp_env->
ss =
ss_double_extended_64;
00501 tmp_fp_env->
es =
es_seventeen_bits;
00502 tmp_fp_env->
simd = 0;
00503
00504 }
else if (pc ==
pc_simd) {
00505 tmp_fp_env->
ss =
ss_single_24;
00506 tmp_fp_env->
es =
es_eight_bits;
00507 tmp_fp_env->
simd = 1;
00508
if (tmp_sf.
controls.
wre)
00509 tmp_sf.
controls.
wre = 0;
00510 tmp_fp_env->
hi_flags.
v = 0;
00511 tmp_fp_env->
hi_flags.
d = 0;
00512 tmp_fp_env->
hi_flags.
z = 0;
00513 tmp_fp_env->
hi_flags.
o = 0;
00514 tmp_fp_env->
hi_flags.
un = 0;
00515 tmp_fp_env->
hi_flags.
i = 0;
00516 tmp_fp_env->
lo_flags.
v = 0;
00517 tmp_fp_env->
lo_flags.
d = 0;
00518 tmp_fp_env->
lo_flags.
z = 0;
00519 tmp_fp_env->
lo_flags.
o = 0;
00520 tmp_fp_env->
lo_flags.
un = 0;
00521 tmp_fp_env->
lo_flags.
i = 0;
00522
00523 }
else if (pc ==
pc_s) {
00524 tmp_fp_env->
ss =
ss_single_24;
00525 tmp_fp_env->
simd = 0;
00526
if (tmp_sf.
controls.
wre)
00527 tmp_fp_env->
es =
es_seventeen_bits;
00528
else
00529 tmp_fp_env->
es =
es_eight_bits;
00530
00531 }
else if (pc ==
pc_d) {
00532 tmp_fp_env->
ss =
ss_double_53;
00533 tmp_fp_env->
simd = 0;
00534
if (tmp_sf.
controls.
wre)
00535 tmp_fp_env->
es =
es_seventeen_bits;
00536
else
00537 tmp_fp_env->
es =
es_eleven_bits;
00538
00539 }
else if (pc ==
pc_sf) {
00540 tmp_fp_env->
simd = 0;
00541
if (tmp_sf.
controls.
pc ==
sf_single)
00542 tmp_fp_env->
ss =
ss_single_24;
00543
else if (tmp_sf.
controls.
pc ==
sf_double)
00544 tmp_fp_env->
ss =
ss_double_53;
00545
else if (tmp_sf.
controls.
pc ==
sf_double_extended)
00546 tmp_fp_env->
ss =
ss_double_extended_64;
00547
00548
if (tmp_sf.
controls.
wre)
00549 tmp_fp_env->
es =
es_seventeen_bits;
00550
else
00551 tmp_fp_env->
es =
es_fifteen_bits;
00552 }
00553
00554
if (sf ==
sf_none) {
00555 tmp_fp_env->
rc =
rc_rz;
00556 tmp_fp_env->
ftz = 0;
00557 }
else {
00558 tmp_fp_env->
rc = tmp_sf.
controls.
rc;
00559 tmp_fp_env->
ftz = tmp_sf.
controls.
ftz && tmp_fp_env->
controls.
ud;
00560 }
00561
00562 tmp_fp_env->
flags.
v = 0;
00563 tmp_fp_env->
flags.
d = 0;
00564 tmp_fp_env->
flags.
z = 0;
00565 tmp_fp_env->
flags.
o = 0;
00566 tmp_fp_env->
flags.
un = 0;
00567 tmp_fp_env->
flags.
i = 0;
00568 tmp_fp_env->
ebc = 0;
00569 tmp_fp_env->
mdl = 0;
00570 tmp_fp_env->
mdh = 0;
00571
00572 tmp_fp_env->
em_faults.
v = 0;
00573 tmp_fp_env->
em_faults.
d = 0;
00574 tmp_fp_env->
em_faults.
z = 0;
00575 tmp_fp_env->
em_faults.
swa = 0;
00576 tmp_fp_env->
em_traps.
i = 0;
00577 tmp_fp_env->
em_traps.
o = 0;
00578 tmp_fp_env->
em_traps.
un = 0;
00579 tmp_fp_env->
fpa = 0;
00580
00581 tmp_fp_env->
hi_faults.
v = 0;
00582 tmp_fp_env->
hi_faults.
d = 0;
00583 tmp_fp_env->
hi_faults.
z = 0;
00584 tmp_fp_env->
hi_faults.
swa = 0;
00585 tmp_fp_env->
hi_traps.
i = 0;
00586 tmp_fp_env->
hi_traps.
o = 0;
00587 tmp_fp_env->
hi_traps.
un = 0;
00588 tmp_fp_env->
hi_fpa = 0;
00589
00590 tmp_fp_env->
lo_faults.
v = 0;
00591 tmp_fp_env->
lo_faults.
d = 0;
00592 tmp_fp_env->
lo_faults.
z = 0;
00593 tmp_fp_env->
lo_faults.
swa = 0;
00594 tmp_fp_env->
lo_traps.
i = 0;
00595 tmp_fp_env->
lo_traps.
o = 0;
00596 tmp_fp_env->
lo_traps.
un = 0;
00597 tmp_fp_env->
lo_fpa = 0;
00598
00599
return;
00600 }
00601
00602
#undef fp_decode_environment
00603 #define fp_decode_environment(arg1, arg2, arg3) \
00604
fp82_fp_decode_environment(ps, arg1, arg2, arg3)
00605
00606
00607
00608
00609
00610
00611
00612
00613
00614
EM_uint_t
00615 fp_reg_disabled(
00616 EM_uint_t f1,
00617 EM_uint_t f2,
00618 EM_uint_t f3,
00619 EM_uint_t f4)
00620 {
00621
EM_uint_t tmp_ret;
00622
EM_uint_t disabled_limit;
00623
00624 tmp_ret=0;
00625 disabled_limit = 31;
00626
00627
if ( ((f1 >= 2) && (f1 <=disabled_limit) && (
PSR.dfl))
00628 || ((f2 >= 2) && (f2 <=disabled_limit) && (
PSR.dfl))
00629 || ((f3 >= 2) && (f3 <=disabled_limit) && (
PSR.dfl))
00630 || ((f4 >= 2) && (f4 <=disabled_limit) && (
PSR.dfl))
00631 )
00632 tmp_ret |= (1<<0);
00633
if ( ((f1 > disabled_limit) && (f1 <= 127) && (
PSR.dfh))
00634 || ((f2 > disabled_limit) && (f2 <= 127) && (
PSR.dfh))
00635 || ((f3 > disabled_limit) && (f3 <= 127) && (
PSR.dfh))
00636 || ((f4 > disabled_limit) && (f4 <= 127) && (
PSR.dfh))
00637 )
00638 tmp_ret |= (1<<1);
00639
return(tmp_ret);
00640 }
00641
00642
INLINE EM_boolean_t
00643 fp_is_nan_or_inf(
EM_fp_reg_type tmp_res)
00644 {
00645
if (
fp_is_nan(tmp_res) ||
fp_is_inf(tmp_res))
00646
return (1);
00647
else
00648
return (0);
00649 }
00650
00651
00652
INLINE EM_fp_reg_type
00653 fp_dp_to_fr(
EM_fp_dp_type tmp_res)
00654 {
00655
EM_fp_reg_type tmp_ret;
00656
00657
if (tmp_res.
exponent == FP_DP_EXP_ONES)
00658 tmp_ret.
exponent = FP_REG_EXP_ONES;
00659
else if (tmp_res.
exponent == 0)
00660 tmp_ret.
exponent = 0;
00661
else
00662 tmp_ret.
exponent = (
EM_uint_t)(((
EM_int_t)tmp_res.
exponent)
00663 - FP_DP_BIAS + FP_REG_BIAS);
00664 tmp_ret.
sign = tmp_res.
sign;
00665 tmp_ret.
significand = tmp_res.
significand.
hi;
00666
return (tmp_ret);
00667 }
00668
00669
00670
00671
00672
00673
00674
00675
INLINE EM_fp_dp_type
00676 fp_add(
EM_fp_dp_type fp_dp,
EM_fp_reg_type fr2,
EM_tmp_fp_env_type tmp_fp_env)
00677
00678 {
00679
EM_fp_dp_type tmp_res;
00680
EM_uint256_t tmp_a, tmp_b, tmp_c;
00681
EM_int_t exp_diff;
00682
EM_uint_t normalize_count;
00683
00684
00685
00686
00687
if (
fp_is_zero_dp(fp_dp) && (
fp_is_zero(fr2) ||
fp_is_pseudo_zero(fr2))) {
00688
00689 tmp_res =
fp_fr_to_dp(FP_ZERO);
00690
if (fp_dp.
sign == fr2.
sign) {
00691 tmp_res.
sign = fr2.
sign;
00692 }
else if (tmp_fp_env.
rc ==
rc_rm) {
00693 tmp_res.
sign = 1;
00694 }
else {
00695 tmp_res.
sign = 0;
00696 }
00697
return(tmp_res);
00698 }
else if (
fp_is_inf_dp(fp_dp)) {
00699
00700
return(fp_dp);
00701 }
else if (
fp_is_inf(fr2)) {
00702
00703
return(
fp_fr_to_dp(fr2));
00704 }
else if(
fp_is_zero_dp(fp_dp)) {
00705
return(
fp_fr_to_dp(fr2));
00706 }
else if(
fp_is_zero(fr2) ||
fp_is_pseudo_zero(fr2) ) {
00707
return(fp_dp);
00708 }
else {
00709
00710 exp_diff = (((
EM_int_t)fp_dp.
exponent) - FP_DP_BIAS )
00711 - (((
EM_int_t)fr2.
exponent) - FP_REG_BIAS);
00712
00713 tmp_res.
sign = fp_dp.
sign;
00714
00715 tmp_a =
fp_U128_to_U256(fp_dp.
significand);
00716 tmp_a =
fp_U256_lsh(tmp_a,64);
00717
00718 tmp_b =
fp_U64_to_U256(fr2.
significand);
00719 tmp_b =
fp_U256_lsh(tmp_b,128);
00720
00721
if (exp_diff >= 0) {
00722 tmp_res.
exponent = fp_dp.
exponent;
00723
00724 tmp_c =
fp_U256_rsh(tmp_b,exp_diff);
00725 tmp_res.
sticky = !
fp_U256_eq(tmp_b,
fp_U256_lsh(tmp_c,exp_diff));
00726 tmp_b = tmp_c;
00727
00728
if(fp_dp.
sign != fr2.
sign) {
00729
00730
if (tmp_res.
sticky)
00731 tmp_b =
fp_U256_inc(tmp_b);
00732
if (fp_dp.
sign)
00733 tmp_a =
fp_U256_neg(tmp_a);
00734
if (fr2.
sign)
00735 tmp_b =
fp_U256_neg(tmp_b);
00736 }
00737 }
else {
00738 tmp_res.
exponent = fp_dp.
exponent - exp_diff;
00739
00740 tmp_c =
fp_U256_rsh(tmp_a,-exp_diff);
00741 tmp_res.
sticky = !
fp_U256_eq(tmp_a,
fp_U256_lsh(tmp_c,-exp_diff));
00742 tmp_a = tmp_c;
00743
00744
if(fp_dp.
sign != fr2.
sign) {
00745
00746
if (tmp_res.
sticky)
00747 tmp_a =
fp_U256_inc(tmp_a);
00748
if (fp_dp.
sign)
00749 tmp_a =
fp_U256_neg(tmp_a);
00750
if (fr2.
sign)
00751 tmp_b =
fp_U256_neg(tmp_b);
00752 }
00753 }
00754
00755 tmp_c =
fp_U256_add(tmp_a, tmp_b);
00756
00757
00758
if (fp_dp.
sign != fr2.
sign) {
00759
if (tmp_c.
hh != 0) {
00760 tmp_res.
sign = 1;
00761 tmp_c =
fp_U256_neg(tmp_c);
00762 }
else {
00763 tmp_res.
sign = 0;
00764 }
00765 }
00766
00767
if (!
fp_U256_eq(tmp_c,U256_0)) {
00768 normalize_count =
fp_U256_lead0(tmp_c);
00769 tmp_res.
exponent -= (normalize_count - 64);
00770 tmp_res.
significand =
fp_U256_to_U128(
00771
fp_U256_rsh(
00772
fp_U256_lsh(tmp_c, normalize_count),
00773 128
00774 )
00775 );
00776
00777
if(normalize_count > 128) {
00778 tmp_res.
sticky |= !
fp_U256_eq(
00779
fp_U256_rsh(
00780
fp_U128_to_U256(tmp_res.
significand),
00781 normalize_count-128
00782 ),
00783 tmp_c
00784 );
00785 }
else {
00786 tmp_res.
sticky |= !
fp_U256_eq(
00787
fp_U256_lsh(
00788
fp_U128_to_U256(tmp_res.
significand),
00789 128-normalize_count
00790 ),
00791 tmp_c
00792 );
00793 }
00794
00795 }
else {
00796
if (fp_dp.
sign == fr2.
sign)
00797 tmp_res.
sign = fp_dp.
sign;
00798
else if (tmp_fp_env.
rc ==
rc_rm)
00799 tmp_res.
sign = 1;
00800
else
00801 tmp_res.
sign = 0;
00802 tmp_res.
exponent = 0;
00803 tmp_res.
significand = U128_0;
00804 }
00805
return(tmp_res);
00806 }
00807 }
00808
00809
00810
00811
00812
00813
00814
00815
00816
INLINE EM_uint_t
00817 fp_single(
EM_fp_reg_type freg)
00818 {
00819
EM_memory_type tmp_mem;
00820 tmp_mem =
fp_fr_to_mem_format(freg, 4, 0);
00821
return (tmp_mem.
uint_32.
uvalue);
00822 }
00823
00824
INLINE void
00825 fp_ieee_to_hilo(
00826 EM_simd_hilo hilo,
00827
EM_tmp_fp_env_type *tmp_fp_env)
00828 {
00829
if(hilo ==
high) {
00830 tmp_fp_env->
hi_flags.
o = tmp_fp_env->
flags.
o;
00831 tmp_fp_env->
flags.
o = 0;
00832
00833 tmp_fp_env->
hi_flags.
un = tmp_fp_env->
flags.
un;
00834 tmp_fp_env->
flags.
un = 0;
00835
00836 tmp_fp_env->
hi_flags.
i = tmp_fp_env->
flags.
i;
00837 tmp_fp_env->
flags.
i = 0;
00838
00839
00840 tmp_fp_env->
hi_traps.
o = tmp_fp_env->
em_traps.
o;
00841 tmp_fp_env->
em_traps.
o = 0;
00842
00843 tmp_fp_env->
hi_traps.
un = tmp_fp_env->
em_traps.
un;
00844 tmp_fp_env->
em_traps.
un = 0;
00845
00846 tmp_fp_env->
hi_traps.
i = tmp_fp_env->
em_traps.
i;
00847 tmp_fp_env->
em_traps.
i = 0;
00848
00849 tmp_fp_env->
hi_faults.
d = tmp_fp_env->
em_faults.
d;
00850 tmp_fp_env->
em_faults.
d = 0;
00851
00852 tmp_fp_env->
hi_faults.
z = tmp_fp_env->
em_faults.
z;
00853 tmp_fp_env->
em_faults.
z = 0;
00854
00855 tmp_fp_env->
hi_faults.
v = tmp_fp_env->
em_faults.
v;
00856 tmp_fp_env->
em_faults.
v = 0;
00857
00858 tmp_fp_env->
hi_fpa = tmp_fp_env->
fpa;
00859 tmp_fp_env->
fpa = 0;
00860
00861 }
else {
00862 tmp_fp_env->
lo_flags.
o = tmp_fp_env->
flags.
o;
00863 tmp_fp_env->
flags.
o = 0;
00864
00865 tmp_fp_env->
lo_flags.
un = tmp_fp_env->
flags.
un;
00866 tmp_fp_env->
flags.
un = 0;
00867
00868 tmp_fp_env->
lo_flags.
i = tmp_fp_env->
flags.
i;
00869 tmp_fp_env->
flags.
i = 0;
00870
00871
00872 tmp_fp_env->
lo_traps.
o = tmp_fp_env->
em_traps.
o;
00873 tmp_fp_env->
em_traps.
o = 0;
00874
00875 tmp_fp_env->
lo_traps.
un = tmp_fp_env->
em_traps.
un;
00876 tmp_fp_env->
em_traps.
un = 0;
00877
00878 tmp_fp_env->
lo_traps.
i = tmp_fp_env->
em_traps.
i;
00879 tmp_fp_env->
em_traps.
i = 0;
00880
00881 tmp_fp_env->
lo_faults.
d = tmp_fp_env->
em_faults.
d;
00882 tmp_fp_env->
em_faults.
d = 0;
00883
00884 tmp_fp_env->
lo_faults.
z = tmp_fp_env->
em_faults.
z;
00885 tmp_fp_env->
em_faults.
z = 0;
00886
00887 tmp_fp_env->
lo_faults.
v = tmp_fp_env->
em_faults.
v;
00888 tmp_fp_env->
em_faults.
v = 0;
00889
00890 tmp_fp_env->
lo_fpa = tmp_fp_env->
fpa;
00891 tmp_fp_env->
fpa = 0;
00892 }
00893 }
00894
00895
EM_fp_reg_type
00896 fp_ieee_round(
00897
EM_fp_dp_type fp_dp,
00898
EM_tmp_fp_env_type *tmp_fp_env)
00899 {
00900
const EM_uint_t FPA[64] = {
00901 0,0,0,1,
00902 0,0,1,1,
00903 0,0,0,1,
00904 0,0,1,1,
00905 0,0,0,0,
00906 0,0,0,0,
00907 0,1,1,1,
00908 0,1,1,1,
00909 0,1,1,1,
00910 0,1,1,1,
00911 0,0,0,0,
00912 0,0,0,0,
00913 0,0,0,0,
00914 0,0,0,0,
00915 0,0,0,0,
00916 0,0,0,0,
00917 };
00918
00919
EM_fp_reg_type tmp_rtn;
00920
EM_fp_dp_type tmp_res, tmp_unbounded_round;
00921
EM_int_t cnt, tmp_shift;
00922
00923
EM_uint_t e_max, e_min,
00924 tmp_unbounded_ebc = 0, tmp_unbounded_fpa = 0;
00925
00926
EM_uint128_t significand_mask;
00927
EM_uint128_t significand_even;
00928
EM_uint128_t significand_round;
00929
EM_uint128_t significand_not_mask;
00930
EM_uint128_t significand_sticky;
00931
00932
00933
00934
00935
00936
00937
00938
if (tmp_fp_env->
es ==
es_eight_bits) {
00939 e_max = FP_DP_BIAS + FP_SGL_BIAS;
00940 e_min = FP_DP_BIAS - FP_SGL_BIAS + 1;
00941 }
else if (tmp_fp_env->
es ==
es_eleven_bits) {
00942 e_max = FP_DP_BIAS + FP_DBL_BIAS;
00943 e_min = FP_DP_BIAS - FP_DBL_BIAS + 1;
00944 }
else if (tmp_fp_env->
es ==
es_fifteen_bits) {
00945 e_max = FP_DP_BIAS + FP_EXT_BIAS;
00946 e_min = FP_DP_BIAS - FP_EXT_BIAS + 1;
00947 }
else if (tmp_fp_env->
es ==
es_seventeen_bits) {
00948 e_max = FP_DP_BIAS + FP_REG_BIAS;
00949 e_min = FP_DP_BIAS - FP_REG_BIAS + 1;
00950 }
00951
00952
00953
00954
00955
00956
00957
if( tmp_fp_env->
ss ==
ss_single_24) {
00958 significand_mask = U128_0xFFFFFF00000000000000000000000000;
00959 significand_even = U128_0x00000100000000000000000000000000;
00960 significand_round = U128_0x00000080000000000000000000000000;
00961 significand_not_mask = U128_0x000000FFFFFFFFFFFFFFFFFFFFFFFFFF;
00962 significand_sticky = U128_0x0000007FFFFFFFFFFFFFFFFFFFFFFFFF;
00963 }
else if( tmp_fp_env->
ss ==
ss_double_53) {
00964 significand_mask = U128_0xFFFFFFFFFFFFF8000000000000000000;
00965 significand_even = U128_0x00000000000008000000000000000000;
00966 significand_round = U128_0x00000000000004000000000000000000;
00967 significand_not_mask = U128_0x00000000000007FFFFFFFFFFFFFFFFFF;
00968 significand_sticky = U128_0x00000000000003FFFFFFFFFFFFFFFFFF;
00969 }
else if( tmp_fp_env->
ss ==
ss_double_extended_64) {
00970 significand_mask = U128_0xFFFFFFFFFFFFFFFF0000000000000000;
00971 significand_even = U128_0x00000000000000010000000000000000;
00972 significand_round = U128_0x00000000000000008000000000000000;
00973 significand_not_mask = U128_0x0000000000000000FFFFFFFFFFFFFFFF;
00974 significand_sticky = U128_0x00000000000000007FFFFFFFFFFFFFFF;
00975 }
00976
00977
00978
00979
00980
00981
if (
fp_is_inf_dp(fp_dp) ) {
00982 tmp_res = fp_dp;
00983 tmp_res.
significand =
fp_U128_band(tmp_res.
significand,
00984 significand_mask);
00985 tmp_rtn =
fp_dp_to_fr(tmp_res);
00986
return(tmp_rtn);
00987
00988
00989
00990
00991
00992 }
else if (
fp_is_nan_dp(fp_dp) ) {
00993 tmp_res = fp_dp;
00994 tmp_res.
significand =
fp_U128_band(tmp_res.
significand,
00995 significand_mask);
00996 tmp_rtn =
fp_dp_to_fr(tmp_res);
00997
return(tmp_rtn);
00998
00999
01000
01001
01002
01003 }
else if (
fp_is_zero_dp(fp_dp) ) {
01004
01005
if ( (fp_dp.
sticky) && (tmp_fp_env->
rc ==
rc_rm) )
01006 tmp_rtn.
sign = 1;
01007
else if ( (fp_dp.
sticky) && (tmp_fp_env->
rc !=
rc_rm) )
01008 tmp_rtn.
sign = 0;
01009
else
01010 tmp_rtn.
sign = fp_dp.
sign;
01011 tmp_rtn.
exponent = fp_dp.
exponent;
01012 tmp_rtn.
significand = 0;
01013
return(tmp_rtn);
01014
01015
01016
01017
01018
01019 }
else {
01020 tmp_res.
sign = fp_dp.
sign;
01021 tmp_res.
exponent = fp_dp.
exponent;
01022 tmp_res.
sticky = fp_dp.
sticky;
01023
01024
01025
01026
01027
01028
01029 cnt = (tmp_fp_env->
rc<<4) | (fp_dp.
sign<<3);
01030
01031 cnt |= !
fp_U128_eq(U128_0,
fp_U128_band(fp_dp.
significand,
01032 significand_even)) << 2;
01033
01034 cnt |= !
fp_U128_eq(U128_0,
fp_U128_band(fp_dp.
significand,
01035 significand_round)) << 1;
01036
01037 tmp_res.
sticky |= !
fp_U128_eq(U128_0,
fp_U128_band(fp_dp.
significand,
01038 significand_sticky));
01039
01040 cnt |= tmp_res.
sticky;
01041 tmp_res.
sticky |= ((cnt&2) != 0);
01042
01043
01044
01045
01046
01047
01048
01049
01050
01051
01052
if (FPA[cnt]) {
01053 tmp_res.
significand =
fp_U128_bor(fp_dp.
significand,
01054 significand_not_mask);
01055 tmp_res.
significand =
fp_U128_inc(tmp_res.
significand);
01056
if (
fp_U128_eq(tmp_res.
significand, U128_0) ) {
01057 tmp_res.
exponent++;
01058 tmp_res.
significand = U128_0x80000000000000000000000000000000;
01059 }
01060 }
else {
01061 tmp_res.
significand =
fp_U128_band(fp_dp.
significand,
01062 significand_mask);
01063 }
01064
01065
01066
01067
01068
01069
01070
if (
fp_U128_eq(tmp_res.
significand, U128_0) ) {
01071 tmp_res.
exponent = 0;
01072 }
01073
01074
01075
01076
01077
01078
01079 tmp_unbounded_round.
sign = tmp_res.
sign;
01080 tmp_unbounded_round.
significand = tmp_res.
significand;
01081 tmp_unbounded_round.
exponent = tmp_res.
exponent;
01082 tmp_unbounded_round.
sticky = tmp_res.
sticky;
01083 tmp_unbounded_fpa = FPA[cnt];
01084
01085
if ( ((tmp_unbounded_round.
exponent>>17)&1)
01086 ^ ((tmp_unbounded_round.
exponent>>16)&1)
01087 )
01088 tmp_unbounded_ebc = 1;
01089
01090 tmp_fp_env->
flags.
i = tmp_res.
sticky;
01091
01092
01093
01094
01095
01096
01097
01098
01099
01100
01101
01102
01103
01104
01105
if ( tmp_res.
exponent > e_max ) {
01106 tmp_fp_env->
flags.
o = 1;
01107
01108
if ( !tmp_fp_env->
controls.
od) {
01109 tmp_fp_env->
ebc = tmp_unbounded_ebc;
01110 tmp_fp_env->
fpa = tmp_unbounded_fpa;
01111 tmp_fp_env->
em_traps.
o = 1;
01112
if(tmp_fp_env->
flags.
i) {
01113 tmp_fp_env->
em_traps.
i = 1;
01114 }
01115
return(
fp_dp_to_fr(tmp_unbounded_round));
01116
01117 }
else {
01118 tmp_res =
fp_max_or_infinity(fp_dp.
sign, tmp_fp_env,
01119 e_max, significand_mask);
01120 tmp_fp_env->
flags.
i = 1;
01121
01122
01123
01124
01125
01126
if ( !tmp_fp_env->
controls.
id ) {
01127 tmp_fp_env->
em_traps.
i = 1;
01128 tmp_fp_env->
fpa =
fp_is_inf_dp(tmp_res);
01129 tmp_fp_env->
ebc = 0;
01130 }
01131
return(
fp_dp_to_fr(tmp_res));
01132 }
01133
01134
01135
01136
01137
01138
01139 }
else if ( tmp_res.
exponent < e_min ) {
01140
01141
01142
01143
01144
01145
01146 tmp_res.
sign = fp_dp.
sign;
01147 tmp_res.
exponent = fp_dp.
exponent;
01148 tmp_res.
sticky = fp_dp.
sticky;
01149
01150
01151
01152
01153
01154
01155
01156
01157
01158 tmp_shift = ((
EM_int_t)e_min) - ((
EM_int_t)fp_dp.
exponent);
01159 tmp_res.
exponent += tmp_shift;
01160
01161
if (tmp_shift >= 128) {
01162 tmp_res.
sticky |= !
fp_U128_eq( fp_dp.
significand, U128_0);
01163 tmp_res.
significand = U128_0;
01164 }
else {
01165 tmp_res.
sticky |= !
fp_U128_eq( U128_0,
01166
fp_U128_lsh(
01167 fp_dp.
significand,
01168 (128-tmp_shift)));
01169 tmp_res.
significand =
fp_U128_rsh(fp_dp.
significand,
01170 tmp_shift);
01171 }
01172
01173
01174
01175
01176
01177
01178 cnt = (tmp_fp_env->
rc<<4) | (tmp_res.
sign<<3);
01179
01180 cnt |= !
fp_U128_eq(U128_0,
fp_U128_band(tmp_res.
significand,
01181 significand_even)) << 2;
01182
01183 cnt |= !
fp_U128_eq(U128_0,
fp_U128_band(tmp_res.
significand,
01184 significand_round)) << 1;
01185
01186 tmp_res.
sticky |= !
fp_U128_eq(U128_0,
fp_U128_band(tmp_res.
significand,
01187 significand_sticky));
01188 cnt |= tmp_res.
sticky;
01189 tmp_res.
sticky |= ((cnt&2) != 0);
01190
01191
01192
01193
01194
01195
01196
01197
01198
01199
01200
if (FPA[cnt]) {
01201 tmp_res.
significand =
fp_U128_bor(tmp_res.
significand,
01202 significand_not_mask);
01203 tmp_res.
significand =
fp_U128_inc(tmp_res.
significand);
01204
if (
fp_U128_eq(tmp_res.
significand, U128_0) ) {
01205 tmp_res.
exponent++;
01206 tmp_res.
significand =
01207 U128_0x80000000000000000000000000000000;
01208 }
01209 }
else {
01210 tmp_res.
significand =
fp_U128_band(tmp_res.
significand,
01211 significand_mask);
01212 }
01213
01214
01215
01216
01217
01218
01219
01220
if (
fp_U128_eq(tmp_res.
significand, U128_0) ) {
01221 tmp_res.
exponent = 0;
01222 }
01223
01224 tmp_fp_env->
flags.
i |= tmp_res.
sticky;
01225
01226
01227
01228
01229
01230
01231
if( tmp_fp_env->
flags.
i )
01232 tmp_fp_env->
flags.
un = 1;
01233
01234
01235
01236
01237
01238
01239
01240
01241
01242
01243
01244
01245
01246
01247
01248
01249
01250
01251
01252 tmp_fp_env->
fpa = FPA[cnt];
01253
if (!tmp_fp_env->
controls.
ud) {
01254 tmp_fp_env->
flags.
un = 1;
01255 tmp_fp_env->
em_traps.
un = 1;
01256 tmp_fp_env->
ebc = tmp_unbounded_ebc;
01257 tmp_fp_env->
fpa = tmp_unbounded_fpa;
01258 tmp_fp_env->
flags.
i = tmp_unbounded_round.
sticky;
01259
if(tmp_fp_env->
flags.
i) {
01260 tmp_fp_env->
em_traps.
i = 1;
01261 }
01262
return(
fp_dp_to_fr(tmp_unbounded_round));
01263 }
01264
else {
01265
if (tmp_fp_env->
ftz) {
01266 tmp_res.
exponent = 0;
01267 tmp_res.
significand = U128_0;
01268 tmp_res.
sticky = 1;
01269 tmp_fp_env->
flags.
i = 1;
01270 tmp_fp_env->
flags.
un = 1;
01271 tmp_fp_env->
ebc = 0;
01272 tmp_fp_env->
fpa = 0;
01273
if (!tmp_fp_env->
controls.
id) {
01274 tmp_fp_env->
em_traps.
i = 1;
01275 }
01276 }
01277
else {
01278
if (!tmp_fp_env->
controls.
id && tmp_fp_env->
flags.
i) {
01279 tmp_fp_env->
fpa = FPA[cnt];
01280 tmp_fp_env->
em_traps.
i = 1;
01281 }
01282 }
01283 }
01284
01285 tmp_rtn =
fp_dp_to_fr(tmp_res);
01286
01287
01288
01289
01290
01291
01292
if ( (tmp_fp_env->
es ==
es_fifteen_bits)
01293 && (tmp_rtn.
exponent == 0x0C001)
01294 &&((tmp_rtn.
significand & U64_0x8000000000000000) == 0) ) {
01295
01296 tmp_rtn.
exponent = 0x00000;
01297 }
01298
01299
return(tmp_rtn);
01300
01301
01302
01303
01304
01305
01306 }
else {
01307
if (!tmp_fp_env->
controls.
id && tmp_fp_env->
flags.
i) {
01308 tmp_fp_env->
fpa = tmp_unbounded_fpa;
01309 tmp_fp_env->
em_traps.
i = 1;
01310 }
01311 tmp_rtn =
fp_dp_to_fr(tmp_unbounded_round);
01312
01313
01314
01315
01316
01317
01318
if ( (tmp_fp_env->
es ==
es_fifteen_bits)
01319 && (tmp_rtn.
exponent == 0x0C001)
01320 &&((tmp_rtn.
significand & U64_0x8000000000000000) == 0) ) {
01321
01322 tmp_rtn.
exponent = 0x00000;
01323 }
01324
01325
return(tmp_rtn);
01326 }
01327 }
01328 }
01329
01330
#undef fp_ieee_round
01331 #define fp_ieee_round(arg1, arg2) fp82_fp_ieee_round(ps, arg1, arg2)
01332
01333
01334
01335
01336
01337
01338
01339
EM_uint_t
01340 fp_ieee_round_sp(
01341
EM_fp_dp_type fp_dp,
01342 EM_simd_hilo hilo,
01343
EM_tmp_fp_env_type *tmp_fp_env)
01344 {
01345
EM_fp_reg_type fp_reg;
01346
EM_memory_type tmp_mem;
01347 fp_reg =
fp_ieee_round( fp_dp, tmp_fp_env);
01348
fp_ieee_to_hilo(hilo, tmp_fp_env);
01349
01350
if( tmp_fp_env->
hi_traps.
un || tmp_fp_env->
hi_traps.
o ||
01351 tmp_fp_env->
lo_traps.
un || tmp_fp_env->
lo_traps.
o ) {
01352
01353 tmp_mem =
fr_to_mem4_bias_adjust(fp_reg);
01354
return (tmp_mem.
uint_32.
uvalue);
01355 }
01356
else {
01357
return (
fp_single(fp_reg));
01358 }
01359 }
01360
01361
#undef fp_ieee_round_sp
01362 #define fp_ieee_round_sp(arg1, arg2, arg3) \
01363
fp82_fp_ieee_round_sp(ps, arg1, arg2, arg3)
01364
01365
01366
EM_fp_reg_type
01367 fp_ieee_rnd_to_int(
01368
EM_fp_reg_type fr1,
01369
EM_tmp_fp_env_type *tmp_fp_env)
01370 {
01371
EM_fp_dp_type tmp_res;
01372
EM_tmp_fp_env_type tmp_fp_env_local;
01373
01374 tmp_res =
fp_fr_to_dp(fr1);
01375 memcpy ((
char *)(&tmp_fp_env_local), (
char *)tmp_fp_env,
01376
sizeof (
EM_tmp_fp_env_type));
01377
01378
if (tmp_res.
exponent < FP_DP_INTEGER_EXP) {
01379
if (tmp_res.
sign) {
01380 tmp_res =
fp_add(tmp_res, FP_NEG_2_TO_63, *tmp_fp_env);
01381 tmp_res =
fp_fr_to_dp(
fp_ieee_round( tmp_res, tmp_fp_env));
01382 tmp_res =
fp_add(tmp_res, FP_POS_2_TO_63, *tmp_fp_env);
01383
return(
fp_ieee_round( tmp_res, &tmp_fp_env_local));
01384 }
else {
01385 tmp_res =
fp_add(tmp_res, FP_POS_2_TO_63, *tmp_fp_env);
01386 tmp_res =
fp_fr_to_dp(
fp_ieee_round( tmp_res, tmp_fp_env));
01387 tmp_res =
fp_add(tmp_res, FP_NEG_2_TO_63, *tmp_fp_env);
01388
return(
fp_ieee_round( tmp_res, &tmp_fp_env_local));
01389 }
01390 }
else
01391
return (fr1);
01392 }
01393
01394
#undef fp_ieee_rnd_to_int
01395 #define fp_ieee_rnd_to_int(arg1,arg2) \
01396
fp82_fp_ieee_rnd_to_int(ps, arg1, arg2)
01397
01398
EM_fp_reg_type
01399 fp_ieee_rnd_to_int_sp(
01400
EM_fp_reg_type fr1,
01401 EM_simd_hilo hilo,
01402
EM_tmp_fp_env_type *tmp_fp_env)
01403 {
01404
EM_fp_reg_type tmp_fix;
01405
EM_tmp_fp_env_type tmp_fp_env_save;
01406
01407 tmp_fp_env_save = *tmp_fp_env;
01408 tmp_fp_env->
ss =
ss_double_extended_64;
01409 tmp_fp_env->es =
es_seventeen_bits;
01410
01411 tmp_fix =
fp_ieee_rnd_to_int(fr1, tmp_fp_env);
01412
01413
fp_ieee_to_hilo(hilo, tmp_fp_env);
01414 tmp_fp_env->ss = tmp_fp_env_save.
ss;
01415 tmp_fp_env->es = tmp_fp_env_save.
es;
01416
return(tmp_fix);
01417 }
01418
01419
01420
01421
01422
01423
01424
01425
01426
01427
01428
INLINE void
01429 fcmp_exception_fault_check(
01430 EM_fp_reg_specifier f2,
01431 EM_fp_reg_specifier f3,
01432 EM_opcode_frel_type frel,
01433 EM_opcode_sf_type sf,
01434
EM_tmp_fp_env_type *tmp_fp_env)
01435 {
01436
EM_fp_reg_type fr2, fr3;
01437
01438 fr2 =
FR[f2];
01439 fr3 =
FR[f3];
01440
01441
fp_decode_environment(
pc_none, sf, tmp_fp_env );
01442
01443
if (
fp_software_assistance_required(ps,
op_fcmp, fr2, fr3)) {
01444 tmp_fp_env->
em_faults.
swa = 1;
01445 }
01446
01447
if (
fp_is_unsupported(fr2) ||
fp_is_unsupported(fr3)) {
01448 tmp_fp_env->
flags.
v = 1;
01449
if (!tmp_fp_env->
controls.
vd) {
01450 tmp_fp_env->
em_faults.
v = 1;
01451 }
01452
01453 }
else if (
fp_is_nan(fr2) ||
fp_is_nan(fr3)) {
01454
if (
fp_is_snan(fr2) ||
fp_is_snan(fr3) ||
01455 (frel ==
frelLT) || (frel ==
frelNLT) ||
01456 (frel ==
frelLE) || (frel ==
frelNLE)) {
01457 tmp_fp_env->
flags.
v = 1;
01458
if (!tmp_fp_env->
controls.
vd) {
01459 tmp_fp_env->
em_faults.
v = 1;
01460 }
01461 }
01462
01463 }
else if (
fp_is_unorm(fr2) ||
fp_is_unorm(fr3)) {
01464 tmp_fp_env->
flags.
d = 1;
01465
if(!tmp_fp_env->
controls.
dd)
01466 tmp_fp_env->
em_faults.
d = 1;
01467 }
01468
01469 }
01470
01471
01472
01473
01474
INLINE void
01475 fpcmp_exception_fault_check(
01476 EM_fp_reg_specifier f2,
01477 EM_fp_reg_specifier f3,
01478 EM_opcode_frel_type frel,
01479 EM_opcode_sf_type sf,
01480
EM_tmp_fp_env_type *tmp_fp_env)
01481 {
01482
EM_fp_reg_type tmp_fr2 =
FR[f2], tmp_fr3 =
FR[f3];
01483
01484
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
01485
01486
01487
01488
01489 tmp_fr2 =
fp_reg_read_hi(f2);
01490 tmp_fr3 =
fp_reg_read_hi(f3);
01491
01492
if (
fp_software_assistance_required(ps,
op_fpcmp, tmp_fr2, tmp_fr3)) {
01493 tmp_fp_env->
hi_faults.
swa = 1;
01494
01495 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
01496
if ((
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
01497 (frel ==
frelLT) || (frel ==
frelNLT) ||
01498 (frel ==
frelLE) || (frel ==
frelNLE))) {
01499 tmp_fp_env->
hi_flags.
v = 1;
01500
if (!tmp_fp_env->
controls.
vd) {
01501 tmp_fp_env->
hi_faults.
v = 1;
01502 }
01503 }
01504
01505
01506 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
01507 tmp_fp_env->
hi_flags.
d = 1;
01508
if (!tmp_fp_env->
controls.
dd)
01509 tmp_fp_env->
hi_faults.
d = 1;
01510 }
01511
01512
01513
01514
01515
01516 tmp_fr2 =
fp_reg_read_lo(f2);
01517 tmp_fr3 =
fp_reg_read_lo(f3);
01518
01519
if (
fp_software_assistance_required(ps,
op_fpcmp, tmp_fr2, tmp_fr3)) {
01520 tmp_fp_env->
lo_faults.
swa = 1;
01521
01522 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
01523
if ((
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
01524 (frel ==
frelLT) || (frel ==
frelNLT) ||
01525 (frel ==
frelLE) || (frel ==
frelNLE))) {
01526 tmp_fp_env->
lo_flags.
v = 1;
01527
if (!tmp_fp_env->
controls.
vd) {
01528 tmp_fp_env->
lo_faults.
v = 1;
01529 }
01530 }
01531
01532
01533 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
01534 tmp_fp_env->
lo_flags.
d = 1;
01535
if (!tmp_fp_env->
controls.
dd)
01536 tmp_fp_env->
lo_faults.
d = 1;
01537 }
01538
return;
01539 }
01540
01541
01542
01543
01544
INLINE EM_fp_reg_type
01545 fcvt_exception_fault_check(
01546 EM_fp_reg_specifier f2,
01547 EM_opcode_sf_type sf,
01548 EM_boolean_t signed_form,
01549 EM_boolean_t trunc_form,
01550
EM_tmp_fp_env_type *tmp_fp_env)
01551 {
01552
EM_fp_reg_type tmp_res, fr2;
01553
EM_tmp_fp_env_type tmp_fp_env_local;
01554
01555 fr2 =
FR[f2];
01556
fp_decode_environment(
pc_none, sf, tmp_fp_env );
01557
if (trunc_form)
01558 tmp_fp_env->
rc =
rc_rz;
01559
01560 tmp_res =
fp_reg_read(fr2);
01561 memcpy ((
char *)(&tmp_fp_env_local), (
char *)tmp_fp_env,
01562
sizeof (
EM_tmp_fp_env_type));
01563 tmp_res =
fp_ieee_rnd_to_int( tmp_res, &tmp_fp_env_local);
01564
01565
if( signed_form &&
fp_software_assistance_required(ps,
op_fcvt_fx, fr2)) {
01566 tmp_fp_env->em_faults.swa = 1;
01567
return (FP_ZERO);
01568
01569 }
else if( !signed_form &&
fp_software_assistance_required(ps,
op_fcvt_fxu, fr2)) {
01570 tmp_fp_env->em_faults.swa = 1;
01571
return (FP_ZERO);
01572 }
01573
01574
if (
fp_is_unsupported(fr2)) {
01575 tmp_fp_env->flags.v = 1;
01576 tmp_res = FP_QNAN;
01577
if (!tmp_fp_env->controls.vd) {
01578 tmp_fp_env->em_faults.v = 1;
01579 }
01580
01581 }
else if (
fp_is_nan(fr2)) {
01582 tmp_fp_env->flags.v = 1;
01583
if (!tmp_fp_env->controls.vd) {
01584 tmp_fp_env->em_faults.v = 1;
01585 }
01586 tmp_res =
fp_is_snan(fr2)?
fp_make_quiet_nan(fr2):fr2;
01587
01588 }
else if ( signed_form &&
01589 (!
fp_lesser_or_equal(FP_NEG_2_TO_63, tmp_res) ||
01590 !
fp_less_than(tmp_res,FP_POS_2_TO_63)) ) {
01591 tmp_fp_env->flags.v = 1;
01592 tmp_res = FP_QNAN;
01593
if (!tmp_fp_env->controls.vd)
01594 tmp_fp_env->em_faults.v = 1;
01595
01596 }
else if ( !signed_form &&
01597 (!
fp_lesser_or_equal(FP_ZERO, tmp_res) ||
01598 !
fp_less_than(tmp_res,FP_POS_2_TO_64)) ) {
01599 tmp_fp_env->flags.v = 1;
01600
if (!tmp_fp_env->controls.vd)
01601 tmp_fp_env->em_faults.v = 1;
01602 tmp_res = FP_QNAN;
01603
01604 }
else if (
fp_is_unorm(fr2)) {
01605 tmp_fp_env->flags.d = 1;
01606
if( !tmp_fp_env->controls.dd)
01607 tmp_fp_env->em_faults.d = 1;
01608 }
01609
01610
return (tmp_res);
01611 }
01612
01613
01614
01615
01616
EM_pair_fp_reg_type
01617 fpcvt_exception_fault_check(
01618 EM_fp_reg_specifier f2,
01619 EM_opcode_sf_type sf,
01620 EM_boolean_t signed_form,
01621 EM_boolean_t trunc_form,
01622
EM_tmp_fp_env_type *tmp_fp_env)
01623 {
01624
EM_tmp_fp_env_type tmp_fp_env_local;
01625
EM_pair_fp_reg_type tmp_reg_pair;
01626
EM_fp_reg_type tmp_fr2 =
FR[f2];
01627
01628
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
01629
01630 tmp_reg_pair.
hi = FP_ZERO;
01631 tmp_reg_pair.
lo = FP_ZERO;
01632
01633
if (trunc_form)
01634 tmp_fp_env->
rc =
rc_rz;
01635
01636
01637
01638
01639 tmp_fr2 =
fp_reg_read_hi(f2);
01640 tmp_fp_env_local = *tmp_fp_env;
01641 tmp_fp_env_local.
ss =
ss_double_extended_64;
01642 tmp_fp_env_local.
es =
es_seventeen_bits;
01643 tmp_reg_pair.
hi =
fp_ieee_rnd_to_int( tmp_fr2, &tmp_fp_env_local);
01644
01645
if ( signed_form &&
01646
fp_software_assistance_required(ps,
op_fpcvt_fx, tmp_fr2)) {
01647 tmp_fp_env->hi_faults.swa = 1;
01648
01649 }
else if( !signed_form &&
01650
fp_software_assistance_required(ps,
op_fpcvt_fxu, tmp_fr2)) {
01651 tmp_fp_env->hi_faults.swa = 1;
01652
01653 }
else if (
fp_is_nan(tmp_fr2)) {
01654 tmp_fp_env->hi_flags.v = 1;
01655 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
01656
if (!tmp_fp_env->controls.vd)
01657 tmp_fp_env->hi_faults.v = 1;
01658
01659
01660 }
else if (signed_form &&
01661 (!
fp_lesser_or_equal(FP_NEG_2_TO_31, tmp_reg_pair.
hi) ||
01662 !
fp_less_than(tmp_reg_pair.
hi,FP_POS_2_TO_31)) ) {
01663 tmp_fp_env->hi_flags.v = 1;
01664 tmp_reg_pair.
hi = FP_QNAN;
01665
if (!tmp_fp_env->controls.vd)
01666 tmp_fp_env->hi_faults.v = 1;
01667
01668 }
else if (!signed_form &&
01669 (!
fp_lesser_or_equal(FP_ZERO, tmp_reg_pair.
hi) ||
01670 !
fp_less_than(tmp_reg_pair.
hi,FP_POS_2_TO_32)) ) {
01671 tmp_fp_env->hi_flags.v = 1;
01672 tmp_reg_pair.
hi = FP_QNAN;
01673
if (!tmp_fp_env->controls.vd)
01674 tmp_fp_env->hi_faults.v = 1;
01675
01676 }
else if (
fp_is_unorm(tmp_fr2)) {
01677 tmp_fp_env->hi_flags.d = 1;
01678
if (!tmp_fp_env->controls.dd)
01679 tmp_fp_env->hi_faults.d = 1;
01680 }
01681
01682
01683
01684
01685 tmp_fr2 =
fp_reg_read_lo(f2);
01686 tmp_fp_env_local = *tmp_fp_env;
01687 tmp_fp_env_local.
ss =
ss_double_extended_64;
01688 tmp_fp_env_local.
es =
es_seventeen_bits;
01689 tmp_reg_pair.
lo =
fp_ieee_rnd_to_int( tmp_fr2, &tmp_fp_env_local);
01690
01691
if ( signed_form &&
01692
fp_software_assistance_required(ps,
op_fpcvt_fx, tmp_fr2)) {
01693 tmp_fp_env->lo_faults.swa = 1;
01694
01695 }
else if( !signed_form &&
01696
fp_software_assistance_required(ps,
op_fpcvt_fxu, tmp_fr2)) {
01697 tmp_fp_env->lo_faults.swa = 1;
01698
01699 }
else if (
fp_is_nan(tmp_fr2)) {
01700 tmp_fp_env->lo_flags.v = 1;
01701 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
01702
if (!tmp_fp_env->controls.vd)
01703 tmp_fp_env->lo_faults.v = 1;
01704
01705 }
else if (signed_form &&
01706 (!
fp_lesser_or_equal(FP_NEG_2_TO_31, tmp_reg_pair.
lo) ||
01707 !
fp_less_than(tmp_reg_pair.
lo,FP_POS_2_TO_31)) ) {
01708 tmp_fp_env->lo_flags.v = 1;
01709 tmp_reg_pair.
lo = FP_QNAN;
01710
if (!tmp_fp_env->controls.vd)
01711 tmp_fp_env->lo_faults.v = 1;
01712
01713 }
else if (!signed_form &&
01714 (!
fp_lesser_or_equal(FP_ZERO, tmp_reg_pair.
lo) ||
01715 !
fp_less_than(tmp_reg_pair.
lo,FP_POS_2_TO_32)) ) {
01716 tmp_fp_env->lo_flags.v = 1;
01717 tmp_reg_pair.
lo = FP_QNAN;
01718
if (!tmp_fp_env->controls.vd)
01719 tmp_fp_env->lo_faults.v = 1;
01720
01721 }
else if (
fp_is_unorm(tmp_fr2)) {
01722 tmp_fp_env->lo_flags.d = 1;
01723
if (!tmp_fp_env->controls.dd)
01724 tmp_fp_env->lo_faults.d = 1;
01725 }
01726
01727
return (tmp_reg_pair);
01728 }
01729
01730
01731
01732
01733
EM_fp_reg_type
01734 fma_exception_fault_check(
01735 EM_fp_reg_specifier f2,
01736 EM_fp_reg_specifier f3,
01737 EM_fp_reg_specifier f4,
01738 EM_opcode_pc_type pc,
01739 EM_opcode_sf_type sf,
01740
EM_tmp_fp_env_type *tmp_fp_env)
01741 {
01742
EM_fp_reg_type tmp_res;
01743
EM_fp_reg_type fr2, fr3, fr4;
01744
01745
01746 fr2 =
FR[f2];
01747 fr3 =
FR[f3];
01748 fr4 =
FR[f4];
01749
01750
01751
01752
01753
fp_decode_environment( pc, sf, tmp_fp_env );
01754
01755
if(f4==1 && f2==0) {
01756
if (
fp_software_assistance_required(ps,
op_fnorm, fr3, *tmp_fp_env)) {
01757 tmp_fp_env->
em_faults.
swa = 1;
01758
return (FP_ZERO);
01759 }
01760 }
else {
01761
if (
fp_software_assistance_required(ps,
op_fma, fr2, fr3, fr4)) {
01762 tmp_fp_env->
em_faults.
swa = 1;
01763
return (FP_ZERO);
01764 }
01765 }
01766
01767 tmp_res = FP_ZERO;
01768
01769
if (
fp_is_unsupported(fr2) ||
fp_is_unsupported(fr3) ||
fp_is_unsupported(fr4)) {
01770 tmp_fp_env->
flags.
v = 1;
01771 tmp_res = FP_QNAN;
01772
if (!tmp_fp_env->
controls.
vd) {
01773 tmp_fp_env->
em_faults.
v = 1;
01774
return (tmp_res);
01775 }
01776
01777 }
else if (
fp_is_nan(fr2) ||
fp_is_nan(fr3) ||
fp_is_nan(fr4)) {
01778
if (
fp_is_snan(fr2) ||
fp_is_snan(fr3) ||
fp_is_snan(fr4)) {
01779 tmp_fp_env->
flags.
v = 1;
01780
if (!tmp_fp_env->
controls.
vd)
01781 tmp_fp_env->
em_faults.
v = 1;
01782 }
01783
01784
if (
fp_is_nan(fr4))
01785 tmp_res =
fp_is_snan(fr4)?
fp_make_quiet_nan(fr4):fr4;
01786
else if (
fp_is_nan(fr2))
01787 tmp_res =
fp_is_snan(fr2)?
fp_make_quiet_nan(fr2):fr2;
01788
else if (
fp_is_nan(fr3))
01789 tmp_res =
fp_is_snan(fr3)?
fp_make_quiet_nan(fr3):fr3;
01790
01791 }
else if ((
fp_is_pos_inf(fr3) &&
fp_is_pos_non_zero(fr4) &&
fp_is_neg_inf(fr2) )
01792 || (
fp_is_pos_inf(fr3) &&
fp_is_neg_non_zero(fr4) &&
fp_is_pos_inf(fr2) )
01793
01794 || (
fp_is_neg_inf(fr3) &&
fp_is_pos_non_zero(fr4) &&
fp_is_pos_inf(fr2) )
01795 || (
fp_is_neg_inf(fr3) &&
fp_is_neg_non_zero(fr4) &&
fp_is_neg_inf(fr2) )
01796
01797 || (
fp_is_pos_non_zero(fr3) &&
fp_is_pos_inf(fr4) &&
fp_is_neg_inf(fr2) )
01798 || (
fp_is_pos_non_zero(fr3) &&
fp_is_neg_inf(fr4) &&
fp_is_pos_inf(fr2) )
01799
01800 || (
fp_is_neg_non_zero(fr3) &&
fp_is_pos_inf(fr4) &&
fp_is_pos_inf(fr2) )
01801 || (
fp_is_neg_non_zero(fr3) &&
fp_is_neg_inf(fr4) &&
fp_is_neg_inf(fr2) )) {
01802
01803 tmp_fp_env->
flags.
v = 1;
01804 tmp_res = FP_QNAN;
01805
if (!tmp_fp_env->
controls.
vd) {
01806 tmp_fp_env->
em_faults.
v = 1;
01807
return (tmp_res);
01808 }
01809
01810 }
else if ((
fp_is_inf(fr3) &&
fp_is_zero(fr4)) || (
fp_is_zero(fr3) &&
fp_is_inf(fr4))) {
01811 tmp_fp_env->
flags.
v = 1;
01812 tmp_res = FP_QNAN;
01813
if (!tmp_fp_env->
controls.
vd) {
01814 tmp_fp_env->
em_faults.
v = 1;
01815
return (tmp_res);
01816 }
01817
01818
01819 }
else if (
fp_is_unorm(fr2) ||
fp_is_unorm(fr3) ||
fp_is_unorm(fr4)) {
01820
01821 tmp_fp_env->
flags.
d = 1;
01822
if(!tmp_fp_env->
controls.
dd) {
01823
01824 tmp_fp_env->
em_faults.
d = 1;
01825 }
01826 }
01827
01828
return (tmp_res);
01829 }
01830
01831
01832
01833
01834
EM_pair_fp_reg_type
01835 fpma_exception_fault_check(
01836 EM_fp_reg_specifier f2,
01837 EM_fp_reg_specifier f3,
01838 EM_fp_reg_specifier f4,
01839 EM_opcode_sf_type sf,
01840
EM_tmp_fp_env_type *tmp_fp_env)
01841 {
01842
EM_pair_fp_reg_type tmp_reg_pair;
01843
EM_fp_reg_type tmp_fr2 =
FR[f2], tmp_fr3 =
FR[f3], tmp_fr4 =
FR[f4];
01844
01845
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
01846
01847 tmp_reg_pair.
hi = FP_ZERO;
01848 tmp_reg_pair.
lo = FP_ZERO;
01849
01850
01851
01852
01853 tmp_fr2 =
fp_reg_read_hi(f2);
01854 tmp_fr3 =
fp_reg_read_hi(f3);
01855 tmp_fr4 =
fp_reg_read_hi(f4);
01856
01857
if (
fp_software_assistance_required(ps,
op_fpma, tmp_fr2, tmp_fr3, tmp_fr4)) {
01858 tmp_fp_env->
hi_faults.
swa = 1;
01859
01860 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3) ||
fp_is_nan(tmp_fr4)) {
01861
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
fp_is_snan(tmp_fr4)) {
01862 tmp_fp_env->
hi_flags.
v = 1;
01863
if (!tmp_fp_env->
controls.
vd)
01864 tmp_fp_env->
hi_faults.
v = 1;
01865 }
01866
01867
if (
fp_is_nan(tmp_fr4))
01868 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr4)?
fp_make_quiet_nan(tmp_fr4):tmp_fr4;
01869
else if (
fp_is_nan(tmp_fr2))
01870 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
01871
else if (
fp_is_nan(tmp_fr3))
01872 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr3)?
fp_make_quiet_nan(tmp_fr3):tmp_fr3;
01873
01874 }
else if ((
fp_is_pos_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
01875 &&
fp_is_neg_inf(tmp_fr2) )
01876 || (
fp_is_pos_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
01877 &&
fp_is_pos_inf(tmp_fr2) )
01878
01879 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
01880 &&
fp_is_pos_inf(tmp_fr2) )
01881 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
01882 &&
fp_is_neg_inf(tmp_fr2) )
01883
01884 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
01885 &&
fp_is_neg_inf(tmp_fr2) )
01886 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
01887 &&
fp_is_pos_inf(tmp_fr2) )
01888
01889 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
01890 &&
fp_is_pos_inf(tmp_fr2) )
01891 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
01892 &&
fp_is_neg_inf(tmp_fr2) )) {
01893 tmp_fp_env->
hi_flags.
v = 1;
01894 tmp_reg_pair.
hi = FP_QNAN;
01895
if (!tmp_fp_env->
controls.
vd)
01896 tmp_fp_env->
hi_faults.
v = 1;
01897
01898 }
else if ((
fp_is_inf(tmp_fr3) &&
fp_is_zero(tmp_fr4))
01899 || (
fp_is_zero(tmp_fr3) &&
fp_is_inf(tmp_fr4))) {
01900 tmp_fp_env->
hi_flags.
v = 1;
01901 tmp_reg_pair.
hi = FP_QNAN;
01902
if (!tmp_fp_env->
controls.
vd)
01903 tmp_fp_env->
hi_faults.
v = 1;
01904
01905
01906 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3) ||
fp_is_unorm(tmp_fr4)) {
01907
01908 tmp_fp_env->
hi_flags.
d = 1;
01909
if (!tmp_fp_env->
controls.
dd)
01910 tmp_fp_env->
hi_faults.
d = 1;
01911 }
01912
01913
01914
01915
01916 tmp_fr2 =
fp_reg_read_lo(f2);
01917 tmp_fr3 =
fp_reg_read_lo(f3);
01918 tmp_fr4 =
fp_reg_read_lo(f4);
01919
01920
if (
fp_software_assistance_required(ps,
op_fpma, tmp_fr2, tmp_fr3, tmp_fr4)) {
01921 tmp_fp_env->
lo_faults.
swa = 1;
01922 }
01923
01924
if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3) ||
fp_is_nan(tmp_fr4)) {
01925
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
fp_is_snan(tmp_fr4)) {
01926 tmp_fp_env->
lo_flags.
v = 1;
01927
if (!tmp_fp_env->
controls.
vd)
01928 tmp_fp_env->
lo_faults.
v = 1;
01929 }
01930
01931
if (
fp_is_nan(tmp_fr4))
01932 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr4)?
fp_make_quiet_nan(tmp_fr4):tmp_fr4;
01933
else if (
fp_is_nan(tmp_fr2))
01934 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
01935
else if (
fp_is_nan(tmp_fr3))
01936 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr3)?
fp_make_quiet_nan(tmp_fr3):tmp_fr3;
01937
01938 }
else if ((
fp_is_pos_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
01939 &&
fp_is_neg_inf(tmp_fr2) )
01940 || (
fp_is_pos_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
01941 &&
fp_is_pos_inf(tmp_fr2) )
01942
01943 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
01944 &&
fp_is_pos_inf(tmp_fr2) )
01945 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
01946 &&
fp_is_neg_inf(tmp_fr2) )
01947
01948 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
01949 &&
fp_is_neg_inf(tmp_fr2) )
01950 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
01951 &&
fp_is_pos_inf(tmp_fr2) )
01952
01953 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
01954 &&
fp_is_pos_inf(tmp_fr2) )
01955 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
01956 &&
fp_is_neg_inf(tmp_fr2) )) {
01957
01958 tmp_fp_env->
lo_flags.
v = 1;
01959 tmp_reg_pair.
lo = FP_QNAN;
01960
if (!tmp_fp_env->
controls.
vd)
01961 tmp_fp_env->
lo_faults.
v = 1;
01962
01963 }
else if ((
fp_is_inf(tmp_fr3) &&
fp_is_zero(tmp_fr4))
01964 || (
fp_is_zero(tmp_fr3) &&
fp_is_inf(tmp_fr4))) {
01965 tmp_fp_env->
lo_flags.
v = 1;
01966 tmp_reg_pair.
lo = FP_QNAN;
01967
if (!tmp_fp_env->
controls.
vd)
01968 tmp_fp_env->
lo_faults.
v = 1;
01969
01970 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3) ||
fp_is_unorm(tmp_fr4)) {
01971 tmp_fp_env->
lo_flags.
d = 1;
01972
if (!tmp_fp_env->
controls.
dd)
01973 tmp_fp_env->
lo_faults.
d = 1;
01974 }
01975
01976
return (tmp_reg_pair);
01977 }
01978
01979
01980
01981
01982
01983
01984
01985
01986
01987
INLINE void
01988 fpminmax_exception_fault_check(
01989 EM_uint_t f2,
01990 EM_uint_t f3,
01991 EM_opcode_sf_type sf,
01992
EM_tmp_fp_env_type *tmp_fp_env)
01993 {
01994
EM_fp_reg_type tmp_fr2 =
FR[f2], tmp_fr3 =
FR[f3];
01995
01996
01997
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
01998
01999
02000
02001
02002
02003 tmp_fr2 =
fp_reg_read_hi(f2);
02004 tmp_fr3 =
fp_reg_read_hi(f3);
02005
02006
if (
fp_software_assistance_required(ps,
op_fpminmax, tmp_fr2, tmp_fr3)) {
02007 tmp_fp_env->
hi_faults.
swa = 1;
02008
02009 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
02010 tmp_fp_env->
hi_flags.
v = 1;
02011
if (!tmp_fp_env->
controls.
vd) {
02012 tmp_fp_env->
hi_faults.
v = 1;
02013 }
02014
02015 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
02016 tmp_fp_env->
hi_flags.
d = 1;
02017
if (!tmp_fp_env->
controls.
dd) {
02018 tmp_fp_env->
hi_faults.
d = 1;
02019 }
02020 }
02021
02022
02023
02024
02025 tmp_fr2 =
fp_reg_read_lo(f2);
02026 tmp_fr3 =
fp_reg_read_lo(f3);
02027
02028
if (
fp_software_assistance_required(ps,
op_fpminmax, tmp_fr2, tmp_fr3)) {
02029 tmp_fp_env->
lo_faults.
swa = 1;
02030
02031 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
02032 tmp_fp_env->
lo_flags.
v = 1;
02033
if (!tmp_fp_env->
controls.
vd) {
02034 tmp_fp_env->
lo_faults.
v = 1;
02035 }
02036
02037
02038 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
02039 tmp_fp_env->
lo_flags.
d = 1;
02040
if (!tmp_fp_env->
controls.
dd)
02041 tmp_fp_env->
lo_faults.
d = 1;
02042 }
02043
02044
return;
02045 }
02046
02047
02048
02049
02050
INLINE void
02051 fminmax_exception_fault_check(
02052 EM_fp_reg_specifier f2,
02053 EM_fp_reg_specifier f3,
02054 EM_opcode_sf_type sf,
02055
EM_tmp_fp_env_type *tmp_fp_env)
02056 {
02057
EM_fp_reg_type fr2, fr3;
02058
02059 fr2 =
FR[f2];
02060 fr3 =
FR[f3];
02061
02062
fp_decode_environment(
pc_none, sf, tmp_fp_env );
02063
02064
if (
fp_software_assistance_required(ps,
op_fminmax, fr2, fr3)) {
02065 tmp_fp_env->
em_faults.
swa = 1;
02066 }
02067
02068
if (
fp_is_unsupported(fr2) ||
fp_is_unsupported(fr3)) {
02069 tmp_fp_env->
flags.
v = 1;
02070
if (!tmp_fp_env->
controls.
vd) {
02071 tmp_fp_env->
em_faults.
v = 1;
02072 }
02073
02074 }
else if (
fp_is_nan(fr2) ||
fp_is_nan(fr3)) {
02075 tmp_fp_env->
flags.
v = 1;
02076
if (!tmp_fp_env->
controls.
vd) {
02077 tmp_fp_env->
em_faults.
v = 1;
02078 }
02079
02080
02081 }
else if (
fp_is_unorm(fr2) ||
fp_is_unorm(fr3)) {
02082 tmp_fp_env->
flags.
d = 1;
02083
if (!tmp_fp_env->
controls.
dd)
02084 tmp_fp_env->
em_faults.
d = 1;
02085 }
02086
02087 }
02088
02089
02090
02091
02092
EM_fp_reg_type
02093 fms_fnma_exception_fault_check(
02094 EM_fp_reg_specifier f2,
02095 EM_fp_reg_specifier f3,
02096 EM_fp_reg_specifier f4,
02097 EM_opcode_pc_type pc,
02098 EM_opcode_sf_type sf,
02099
EM_tmp_fp_env_type *tmp_fp_env)
02100 {
02101
EM_fp_reg_type fr2, fr3, fr4;
02102
EM_fp_reg_type tmp_res;
02103
02104 fr2 =
FR[f2];
02105 fr3 =
FR[f3];
02106 fr4 =
FR[f4];
02107
02108
fp_decode_environment( pc, sf, tmp_fp_env );
02109
02110
if (
fp_software_assistance_required(ps,
op_fms_fnma, fr2, fr3, fr4)) {
02111 tmp_fp_env->
em_faults.
swa = 1;
02112
return (FP_ZERO);
02113 }
02114
02115 tmp_res = FP_ZERO;
02116
02117
if (
fp_is_unsupported(fr2) ||
fp_is_unsupported(fr3) ||
fp_is_unsupported(fr4)) {
02118 tmp_fp_env->
flags.
v = 1;
02119 tmp_res = FP_QNAN;
02120
if (!tmp_fp_env->
controls.
vd) {
02121 tmp_fp_env->
em_faults.
v = 1;
02122
return (tmp_res);
02123 }
02124
02125 }
else if (
fp_is_nan(fr2) ||
fp_is_nan(fr3) ||
fp_is_nan(fr4)) {
02126
if (
fp_is_snan(fr2) ||
fp_is_snan(fr3) ||
fp_is_snan(fr4)) {
02127 tmp_fp_env->
flags.
v = 1;
02128
if (!tmp_fp_env->
controls.
vd)
02129 tmp_fp_env->
em_faults.
v = 1;
02130 }
02131
02132
02133
if (
fp_is_nan(fr4))
02134 tmp_res =
fp_is_snan(fr4)?
fp_make_quiet_nan(fr4):fr4;
02135
else if (
fp_is_nan(fr2))
02136 tmp_res =
fp_is_snan(fr2)?
fp_make_quiet_nan(fr2):fr2;
02137
else if (
fp_is_nan(fr3))
02138 tmp_res =
fp_is_snan(fr3)?
fp_make_quiet_nan(fr3):fr3;
02139
02140 }
else if ((
fp_is_pos_inf(fr3) &&
fp_is_pos_non_zero(fr4) &&
fp_is_pos_inf(fr2) )
02141 || (
fp_is_pos_inf(fr3) &&
fp_is_neg_non_zero(fr4) &&
fp_is_neg_inf(fr2) )
02142 || (
fp_is_neg_inf(fr3) &&
fp_is_pos_non_zero(fr4) &&
fp_is_neg_inf(fr2) )
02143 || (
fp_is_neg_inf(fr3) &&
fp_is_neg_non_zero(fr4) &&
fp_is_pos_inf(fr2) )
02144 || (
fp_is_pos_non_zero(fr3) &&
fp_is_pos_inf(fr4) &&
fp_is_pos_inf(fr2) )
02145 || (
fp_is_pos_non_zero(fr3) &&
fp_is_neg_inf(fr4) &&
fp_is_neg_inf(fr2) )
02146 || (
fp_is_neg_non_zero(fr3) &&
fp_is_pos_inf(fr4) &&
fp_is_neg_inf(fr2) )
02147 || (
fp_is_neg_non_zero(fr3) &&
fp_is_neg_inf(fr4) &&
fp_is_pos_inf(fr2) )) {
02148 tmp_fp_env->
flags.
v = 1;
02149 tmp_res = FP_QNAN;
02150
if (!tmp_fp_env->
controls.
vd) {
02151 tmp_fp_env->
em_faults.
v = 1;
02152
return (tmp_res);
02153 }
02154
02155 }
else if ((
fp_is_inf(fr3) &&
fp_is_zero(fr4)) || (
fp_is_zero(fr3) &&
fp_is_inf(fr4))) {
02156 tmp_fp_env->
flags.
v = 1;
02157 tmp_res = FP_QNAN;
02158
if (!tmp_fp_env->
controls.
vd) {
02159 tmp_fp_env->
em_faults.
v = 1;
02160
return (tmp_res);
02161 }
02162
02163
02164 }
else if (
fp_is_unorm(fr2) ||
fp_is_unorm(fr3) ||
fp_is_unorm(fr4)) {
02165 tmp_fp_env->
flags.
d = 1;
02166
if (!tmp_fp_env->
controls.
dd)
02167 tmp_fp_env->
em_faults.
d = 1;
02168 }
02169
02170
return (tmp_res);
02171 }
02172
02173
02174
02175
02176
EM_pair_fp_reg_type
02177 fpms_fpnma_exception_fault_check(
02178 EM_fp_reg_specifier f2,
02179 EM_fp_reg_specifier f3,
02180 EM_fp_reg_specifier f4,
02181 EM_opcode_sf_type sf,
02182
EM_tmp_fp_env_type *tmp_fp_env)
02183 {
02184
EM_pair_fp_reg_type tmp_reg_pair;
02185
EM_fp_reg_type tmp_fr2 =
FR[f2], tmp_fr3 =
FR[f3], tmp_fr4 =
FR[f4];
02186
02187
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
02188
02189 tmp_reg_pair.
hi = FP_ZERO;
02190 tmp_reg_pair.
lo = FP_ZERO;
02191
02192
02193
02194
02195 tmp_fr2 =
fp_reg_read_hi(f2);
02196 tmp_fr3 =
fp_reg_read_hi(f3);
02197 tmp_fr4 =
fp_reg_read_hi(f4);
02198
02199
if (
fp_software_assistance_required(ps,
op_fpms_fpnma, tmp_fr2, tmp_fr3, tmp_fr4)) {
02200 tmp_fp_env->
hi_faults.
swa = 1;
02201
02202 }
else if (
fp_is_unsupported(tmp_fr2) ||
fp_is_unsupported(tmp_fr3) ||
fp_is_unsupported(tmp_fr4)) {
02203 tmp_fp_env->
hi_flags.
v = 1;
02204 tmp_reg_pair.
hi = FP_QNAN;
02205
if (!tmp_fp_env->
controls.
vd)
02206 tmp_fp_env->
hi_faults.
v = 1;
02207
02208 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3) ||
fp_is_nan(tmp_fr4)) {
02209
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
fp_is_snan(tmp_fr4)) {
02210 tmp_fp_env->
hi_flags.
v = 1;
02211
if (!tmp_fp_env->
controls.
vd)
02212 tmp_fp_env->
hi_faults.
v = 1;
02213 }
02214
02215
if (
fp_is_nan(tmp_fr4))
02216 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr4)?
fp_make_quiet_nan(tmp_fr4):tmp_fr4;
02217
else if (
fp_is_nan(tmp_fr2))
02218 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
02219
else if (
fp_is_nan(tmp_fr3))
02220 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr3)?
fp_make_quiet_nan(tmp_fr3):tmp_fr3;
02221
02222 }
else if ((
fp_is_pos_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
02223 &&
fp_is_pos_inf(tmp_fr2) )
02224 || (
fp_is_pos_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
02225 &&
fp_is_neg_inf(tmp_fr2) )
02226 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
02227 &&
fp_is_neg_inf(tmp_fr2) )
02228 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
02229 &&
fp_is_pos_inf(tmp_fr2) )
02230 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
02231 &&
fp_is_pos_inf(tmp_fr2) )
02232 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
02233 &&
fp_is_neg_inf(tmp_fr2) )
02234 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
02235 &&
fp_is_neg_inf(tmp_fr2) )
02236 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
02237 &&
fp_is_pos_inf(tmp_fr2) )) {
02238 tmp_fp_env->
hi_flags.
v = 1;
02239 tmp_reg_pair.
hi = FP_QNAN;
02240
if (!tmp_fp_env->
controls.
vd)
02241 tmp_fp_env->
hi_faults.
v = 1;
02242
02243 }
else if ((
fp_is_inf(tmp_fr3) &&
fp_is_zero(tmp_fr4))
02244 || (
fp_is_zero(tmp_fr3) &&
fp_is_inf(tmp_fr4))) {
02245 tmp_fp_env->
hi_flags.
v = 1;
02246 tmp_reg_pair.
hi = FP_QNAN;
02247
if (!tmp_fp_env->
controls.
vd)
02248 tmp_fp_env->
hi_faults.
v = 1;
02249
02250 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3) ||
fp_is_unorm(tmp_fr4)) {
02251 tmp_fp_env->
hi_flags.
d = 1;
02252
if (!tmp_fp_env->
controls.
dd)
02253 tmp_fp_env->
hi_faults.
d = 1;
02254 }
02255
02256
02257
02258
02259 tmp_fr2 =
fp_reg_read_lo(f2);
02260 tmp_fr3 =
fp_reg_read_lo(f3);
02261 tmp_fr4 =
fp_reg_read_lo(f4);
02262
02263
if (
fp_software_assistance_required(ps,
op_fpms_fpnma, tmp_fr2, tmp_fr3, tmp_fr4)) {
02264 tmp_fp_env->
lo_faults.
swa = 1;
02265
02266 }
else if (
fp_is_unsupported(tmp_fr2) ||
fp_is_unsupported(tmp_fr3) ||
fp_is_unsupported(tmp_fr4)) {
02267 tmp_fp_env->
lo_flags.
v = 1;
02268 tmp_reg_pair.
lo = FP_QNAN;
02269
if (!tmp_fp_env->
controls.
vd)
02270 tmp_fp_env->
lo_faults.
v = 1;
02271
02272 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3) ||
fp_is_nan(tmp_fr4)) {
02273
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3) ||
fp_is_snan(tmp_fr4)) {
02274 tmp_fp_env->
lo_flags.
v = 1;
02275
if (!tmp_fp_env->
controls.
vd)
02276 tmp_fp_env->
lo_faults.
v = 1;
02277 }
02278
02279
if (
fp_is_nan(tmp_fr4))
02280 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr4)?
fp_make_quiet_nan(tmp_fr4):tmp_fr4;
02281
else if (
fp_is_nan(tmp_fr2))
02282 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr2)?
fp_make_quiet_nan(tmp_fr2):tmp_fr2;
02283
else if (
fp_is_nan(tmp_fr3))
02284 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr3)?
fp_make_quiet_nan(tmp_fr3):tmp_fr3;
02285
02286 }
else if ((
fp_is_pos_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
02287 &&
fp_is_pos_inf(tmp_fr2) )
02288 || (
fp_is_pos_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
02289 &&
fp_is_neg_inf(tmp_fr2) )
02290 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_pos_non_zero(tmp_fr4)
02291 &&
fp_is_neg_inf(tmp_fr2) )
02292 || (
fp_is_neg_inf(tmp_fr3) &&
fp_is_neg_non_zero(tmp_fr4)
02293 &&
fp_is_pos_inf(tmp_fr2) )
02294 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
02295 &&
fp_is_pos_inf(tmp_fr2) )
02296 || (
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
02297 &&
fp_is_neg_inf(tmp_fr2) )
02298 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_pos_inf(tmp_fr4)
02299 &&
fp_is_neg_inf(tmp_fr2) )
02300 || (
fp_is_neg_non_zero(tmp_fr3) &&
fp_is_neg_inf(tmp_fr4)
02301 &&
fp_is_pos_inf(tmp_fr2) )) {
02302 tmp_fp_env->
lo_flags.
v = 1;
02303 tmp_reg_pair.
lo = FP_QNAN;
02304
if (!tmp_fp_env->
controls.
vd)
02305 tmp_fp_env->
lo_faults.
v = 1;
02306
02307 }
else if ((
fp_is_inf(tmp_fr3) &&
fp_is_zero(tmp_fr4))
02308 || (
fp_is_zero(tmp_fr3) &&
fp_is_inf(tmp_fr4))) {
02309 tmp_fp_env->
lo_flags.
v = 1;
02310 tmp_reg_pair.
lo = FP_QNAN;
02311
if (!tmp_fp_env->
controls.
vd)
02312 tmp_fp_env->
lo_faults.
v = 1;
02313
02314 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3) ||
fp_is_unorm(tmp_fr4)) {
02315 tmp_fp_env->
lo_flags.
d = 1;
02316
if (!tmp_fp_env->
controls.
dd)
02317 tmp_fp_env->
lo_faults.
d = 1;
02318 }
02319
02320
return (tmp_reg_pair);
02321 }
02322
02323
02324
02325
INLINE EM_fp_dp_type
02326 fp_max_or_infinity(EM_uint_t sign,
EM_tmp_fp_env_type *tmp_fp_env,
02327 EM_uint_t e_max,
EM_uint128_t max_significand)
02328 {
02329
EM_fp_dp_type tmp_res;
02330 tmp_res.
sign = sign;
02331
02332
if (tmp_fp_env->
rc ==
rc_rm) {
02333
if (tmp_res.
sign) {
02334 tmp_res.
exponent = FP_DP_EXP_ONES;
02335 tmp_res.
significand = U128_0x80000000000000000000000000000000;
02336 }
else {
02337 tmp_res.
exponent = e_max;
02338 tmp_res.
significand = max_significand;
02339 }
02340
02341 }
else if (tmp_fp_env->
rc ==
rc_rz) {
02342 tmp_res.
exponent = e_max;
02343 tmp_res.
significand = max_significand;
02344
02345 }
else if (tmp_fp_env->
rc ==
rc_rp) {
02346
if (tmp_res.
sign) {
02347 tmp_res.
exponent = e_max;
02348 tmp_res.
significand = max_significand;
02349 }
else {
02350 tmp_res.
exponent = FP_DP_EXP_ONES;
02351 tmp_res.
significand = U128_0x80000000000000000000000000000000;
02352 }
02353
02354 }
else {
02355 tmp_res.
exponent = FP_DP_EXP_ONES;
02356 tmp_res.
significand = U128_0x80000000000000000000000000000000;
02357 }
02358
02359
return(tmp_res);
02360 }
02361
02362
INLINE EM_fp_dp_type
02363 fp_mul(
EM_fp_reg_type fr3,
EM_fp_reg_type fr4)
02364 {
02365
EM_fp_dp_type tmp_res;
02366
EM_int_t normalize_count;
02367
02368
02369
02370
02371
if (
fp_is_zero(fr3) ||
fp_is_zero(fr4)) {
02372
02373 tmp_res =
fp_fr_to_dp(FP_ZERO);
02374 tmp_res.
sign = fr3.
sign ^ fr4.
sign;
02375 }
else if (
fp_is_inf(fr3) ||
fp_is_inf(fr4)) {
02376
02377 tmp_res =
fp_fr_to_dp(FP_INFINITY);
02378 tmp_res.
sign = fr3.
sign ^ fr4.
sign;
02379 }
else if (
fp_is_pseudo_zero(fr3) ||
fp_is_pseudo_zero(fr4)) {
02380
02381
02382 tmp_res =
fp_fr_to_dp(FP_ZERO);
02383 tmp_res.
sign = fr3.
sign ^ fr4.
sign;
02384 }
else {
02385
02386 tmp_res.
sign = fr3.
sign ^ fr4.
sign;
02387 tmp_res.
exponent = (
EM_uint_t)(
02388 (((
EM_int_t)fr3.
exponent)-FP_REG_BIAS)
02389 + (((
EM_int_t)fr4.
exponent)-FP_REG_BIAS)
02390 + FP_DP_BIAS);
02391
02392
02393 tmp_res.
significand =
fp_U64_x_U64_to_U128(fr3.
significand,
02394 fr4.
significand);
02395
if (
fp_U128_lead0(tmp_res.
significand) == 0) {
02396
02397
02398 tmp_res.
exponent += 1;
02399
02400
02401 }
else if (
fp_U128_lead0(tmp_res.
significand) == 1) {
02402
02403
02404 tmp_res.
significand =
fp_U128_lsh(tmp_res.
significand,1);
02405
02406 }
else {
02407
02408
02409 normalize_count =
fp_U128_lead0(tmp_res.
significand);
02410 tmp_res.
exponent -= normalize_count-1;
02411 tmp_res.
significand =
fp_U128_lsh(tmp_res.
significand,
02412 normalize_count);
02413 }
02414 }
02415 tmp_res.
sticky = 0;
02416
return(tmp_res);
02417 }
02418
02419
INLINE EM_fp_reg_type
02420 fp_normalize(
EM_fp_reg_type freg)
02421 {
02422
EM_int_t tmp_normalize_count;
02423
02424
if (
fp_is_nan(freg) ||
fp_is_inf(freg) ||
fp_is_normal(freg)
02425 ||
fp_is_unsupported(freg) ||
fp_is_zero(freg) ||
fp_is_natval(freg))
02426
return (freg);
02427
02428 tmp_normalize_count =
fp_U64_lead0(freg.
significand);
02429
if (tmp_normalize_count == 64) {
02430
if(freg.
exponent)
02431 freg.
exponent = 0;
02432
return (freg);
02433 }
else if(freg.
exponent == 1) {
02434
return(freg);
02435
02436
02437 }
else if ((((
EM_int_t)freg.
exponent) - tmp_normalize_count) <= 0) {
02438 tmp_normalize_count = freg.
exponent -1;
02439 freg.
exponent = 1;
02440 freg.
significand <<= tmp_normalize_count;
02441
return (freg);
02442
02443 }
else {
02444 freg.
exponent -= tmp_normalize_count;
02445 freg.
significand <<= tmp_normalize_count;
02446
return(freg);
02447 }
02448 }
02449
02450
INLINE EM_fp_dp_type
02451 fp_normalize_dp(
EM_fp_dp_type fp_dp)
02452 {
02453
EM_int_t tmp_normalize_count;
02454
02455
if (
fp_is_nan_dp(fp_dp) ||
fp_is_inf_dp(fp_dp) ||
fp_is_normal_dp(fp_dp)
02456 ||
fp_is_zero_dp(fp_dp))
02457
return (fp_dp);
02458
else if (
fp_is_unsupported_dp(fp_dp))
02459
return (
fp_fr_to_dp(FP_QNAN));
02460 tmp_normalize_count =
fp_U128_lead0(fp_dp.
significand);
02461
if (tmp_normalize_count == 128) {
02462
if (fp_dp.
exponent)
02463 fp_dp.
exponent = 0;
02464
return (fp_dp);
02465
02466 }
else if ((((
EM_int_t)fp_dp.
exponent) - tmp_normalize_count) <= 0) {
02467
02468 fp_dp.
exponent = 0;
02469 fp_dp.
significand = U128_0;
02470
return (fp_dp);
02471 }
else {
02472 fp_dp.
exponent -= tmp_normalize_count;
02473 fp_dp.
significand =
fp_U128_lsh(fp_dp.
significand,
02474 tmp_normalize_count);
02475
return(fp_dp);
02476 }
02477 }
02478
02479
02480
EM_fp_dp_type
02481 fp82_fp_fr_to_dp(
EM_fp_reg_type fr1)
02482 {
02483
EM_fp_dp_type tmp_res;
02484 tmp_res.
sign = fr1.
sign;
02485
if (fr1.
exponent == 0)
02486 tmp_res.
exponent = 0;
02487
else if (fr1.
exponent == FP_REG_EXP_ONES)
02488 tmp_res.
exponent = FP_DP_EXP_ONES;
02489
else
02490 tmp_res.
exponent = (
EM_uint_t)(((
EM_int_t)fr1.
exponent)
02491 - FP_REG_BIAS + FP_DP_BIAS);
02492
02493 tmp_res.
significand.
hi = fr1.
significand;
02494 tmp_res.
significand.
lo = U64_0;
02495 tmp_res.
sticky = 0;
02496
return(
fp_normalize_dp(tmp_res));
02497 }
02498
02499
02500
02501
02502
EM_fp_reg_type
02503 frcpa_exception_fault_check(
02504 EM_fp_reg_specifier f2,
02505 EM_fp_reg_specifier f3,
02506 EM_opcode_sf_type sf,
02507
EM_tmp_fp_env_type *tmp_fp_env)
02508 {
02509
EM_fp_reg_type fr2, fr3;
02510
EM_fp_reg_type tmp_res;
02511
EM_int_t estimated_exponent;
02512
02513 fr2 =
FR[f2];
02514 fr3 =
FR[f3];
02515
fp_decode_environment(
pc_none, sf, tmp_fp_env );
02516
02517
if (
fp_software_assistance_required(ps,
op_frcpa, fr2, fr3) ) {
02518 tmp_fp_env->
em_faults.
swa = 1;
02519
return (FP_ZERO);
02520 }
02521
02522 tmp_res = FP_ZERO;
02523
02524
if (
fp_is_unsupported(fr2) ||
fp_is_unsupported(fr3)) {
02525 tmp_fp_env->
flags.
v = 1;
02526 tmp_res = FP_QNAN;
02527
02528
if (!tmp_fp_env->
controls.
vd) {
02529 tmp_fp_env->
em_faults.
v = 1;
02530 }
02531
02532 }
else if (
fp_is_nan(fr2) ||
fp_is_nan(fr3)) {
02533
if (
fp_is_snan(fr2) ||
fp_is_snan(fr3)) {
02534 tmp_fp_env->
flags.
v = 1;
02535
if (!tmp_fp_env->
controls.
vd) {
02536 tmp_fp_env->
em_faults.
v = 1;
02537 }
02538 }
02539
if (
fp_is_nan(fr2)) {
02540 tmp_res =
fp_is_snan(fr2)?
fp_make_quiet_nan(fr2):fr2;
02541 }
else if (
fp_is_nan(fr3)) {
02542 tmp_res =
fp_is_snan(fr3)?
fp_make_quiet_nan(fr3):fr3;
02543 }
02544
02545 }
else if ( (
fp_is_inf(fr2) &&
fp_is_inf(fr3))
02546 || ( (
fp_is_zero(fr2) ||
fp_is_pseudo_zero(fr2))
02547 && (
fp_is_zero(fr3) ||
fp_is_pseudo_zero(fr3)) ) ) {
02548 tmp_fp_env->
flags.
v = 1;
02549 tmp_res = FP_QNAN;
02550
if (!tmp_fp_env->
controls.
vd) {
02551 tmp_fp_env->
em_faults.
v = 1;
02552 }
02553
02554 }
else if ( ( (
fp_is_normal(fr2) && !
fp_is_zero(fr2) )
02555 || (
fp_is_unorm(fr2) && !
fp_is_pseudo_zero(fr2) ) )
02556 && (
fp_is_zero(fr3) ||
fp_is_pseudo_zero(fr3) ) ) {
02557 tmp_fp_env->
flags.
z = 1;
02558 tmp_res = FP_INFINITY;
02559 tmp_res.
sign = fr2.
sign ^ fr3.
sign;
02560
if (!tmp_fp_env->
controls.
zd) {
02561 tmp_fp_env->
em_faults.
z = 1;
02562 }
02563
02564
02565 }
else if (
fp_is_unorm(fr2) ||
fp_is_unorm(fr3)) {
02566 tmp_fp_env->
flags.
d = 1;
02567
if (!tmp_fp_env->
controls.
dd) {
02568 tmp_fp_env->
em_faults.
d = 1;
02569 }
02570 }
02571
02572
02573
02574
02575
02576
02577
02578
02579
02580
02581
if ( !
fp_is_zero(fr2) &&
fp_is_finite(fr2) && !
fp_is_pseudo_zero(fr2)
02582 && !
fp_is_zero(fr3) &&
fp_is_finite(fr3) && !
fp_is_pseudo_zero(fr3)
02583 ) {
02584
02585 fr2 =
fp_normalize(
fp_reg_read(fr2));
02586 fr3 =
fp_normalize(
fp_reg_read(fr3));
02587
02588 estimated_exponent = (
EM_int_t)(fr2.
exponent)
02589 - (
EM_int_t)(fr3.
exponent);
02590
02591
if (
fp_is_unorm(fr3)
02592 || ( fr3.
exponent >= (FP_REG_BIAS+FP_REG_BIAS-2) )
02593 || ( estimated_exponent >= ((
EM_int_t)(FP_REG_BIAS)) )
02594 || ( estimated_exponent <= (2 - (
EM_int_t)FP_REG_BIAS) )
02595 || ( fr2.
exponent <= (
ss_double_extended_64) )
02596 ) {
02597 tmp_fp_env->
em_faults.
swa = 1;
02598 }
02599 }
02600
return (tmp_res);
02601 }
02602
02603
02604
02605
02606
EM_pair_fp_reg_type
02607 fprcpa_exception_fault_check(
02608 EM_fp_reg_specifier f2,
02609 EM_fp_reg_specifier f3,
02610 EM_opcode_sf_type sf,
02611
EM_tmp_fp_env_type *tmp_fp_env,
02612
EM_limits_check_fprcpa *limits_check)
02613 {
02614
EM_pair_fp_reg_type tmp_reg_pair;
02615
EM_fp_reg_type tmp_fr2 =
FR[f2], tmp_fr3 =
FR[f3];
02616
EM_int_t estimated_exponent;
02617
02618
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
02619
02620 tmp_reg_pair.
hi = FP_ZERO;
02621 tmp_reg_pair.
lo = FP_ZERO;
02622
02623
02624
02625
02626 tmp_fr2 =
fp_reg_read_hi(f2);
02627 tmp_fr3 =
fp_reg_read_hi(f3);
02628
02629
if (
fp_software_assistance_required(ps,
op_fprcpa, tmp_fr2, tmp_fr3)) {
02630 tmp_fp_env->
hi_faults.
swa = 1;
02631
02632 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
02633
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3)) {
02634 tmp_fp_env->
hi_flags.
v = 1;
02635
if (!tmp_fp_env->
controls.
vd) {
02636 tmp_fp_env->
hi_faults.
v = 1;
02637 }
02638 }
02639
if (
fp_is_nan(tmp_fr2)) {
02640 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr2)
02641 ?
fp_make_quiet_nan(tmp_fr2) : tmp_fr2;
02642 }
else if (
fp_is_nan(tmp_fr3)) {
02643 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr3)
02644 ?
fp_make_quiet_nan(tmp_fr3) : tmp_fr3;
02645 }
02646
02647
02648
02649
02650 }
else if ( (
fp_is_inf(tmp_fr2) &&
fp_is_inf(tmp_fr3) )
02651 || (
fp_is_zero(tmp_fr2) &&
fp_is_zero(tmp_fr3) ) ) {
02652 tmp_fp_env->
hi_flags.
v = 1;
02653 tmp_reg_pair.
hi = FP_QNAN;
02654
if (!tmp_fp_env->
controls.
vd) {
02655 tmp_fp_env->
hi_faults.
v = 1;
02656 }
02657
02658
02659
02660
02661
02662 }
else if ( !
fp_is_inf(tmp_fr2) && !
fp_is_zero(tmp_fr2) &&
fp_is_zero(tmp_fr3) ) {
02663 tmp_fp_env->
hi_flags.
z = 1;
02664 tmp_reg_pair.
hi = FP_INFINITY;
02665 tmp_reg_pair.
hi.
sign = tmp_fr2.
sign ^ tmp_fr3.
sign;
02666
if (!tmp_fp_env->
controls.
zd) {
02667 tmp_fp_env->
hi_faults.
z = 1;
02668 }
02669
02670 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
02671 tmp_fp_env->
hi_flags.
d = 1;
02672
if (!tmp_fp_env->
controls.
dd) {
02673 tmp_fp_env->
hi_faults.
d = 1;
02674 }
02675 }
02676
02677
if ( !
fp_is_zero(tmp_fr2) &&
fp_is_finite(tmp_fr2)
02678 && !
fp_is_zero(tmp_fr3) &&
fp_is_finite(tmp_fr3) ) {
02679
02680 tmp_fr2 =
fp_normalize(tmp_fr2);
02681
02682
if (
fp_is_unorm(tmp_fr3) ) {
02683 limits_check->
hi_fr3 = 1;
02684 tmp_reg_pair.
hi = FP_INFINITY;
02685 tmp_reg_pair.
hi.
sign = tmp_fr3.
sign;
02686 tmp_fr3 =
fp_normalize(tmp_fr3);
02687
02688 }
else if ( tmp_fr3.
exponent >= (FP_REG_BIAS+FP_SGL_BIAS-2) ) {
02689 limits_check->
hi_fr3 = 1;
02690 tmp_reg_pair.
hi = FP_ZERO;
02691 tmp_reg_pair.
hi.
sign = tmp_fr3.
sign;
02692 }
02693
02694 estimated_exponent = (
EM_int_t)tmp_fr2.
exponent
02695 - (
EM_int_t)tmp_fr3.
exponent;
02696
02697
02698
if ( (estimated_exponent >= (((
EM_int_t)(FP_SGL_BIAS))) )
02699 || (estimated_exponent <= (2-((
EM_int_t)FP_SGL_BIAS)) )
02700 || (tmp_fr2.
exponent <= (
ss_single_24+FP_REG_BIAS-FP_SGL_BIAS) )
02701 ) {
02702 limits_check->
hi_fr2_or_quot = 1;
02703 }
02704 }
02705
02706
02707
02708
02709 tmp_fr2 =
fp_reg_read_lo(f2);
02710 tmp_fr3 =
fp_reg_read_lo(f3);
02711
02712
if (
fp_software_assistance_required(ps,
op_fprcpa, tmp_fr2, tmp_fr3)) {
02713 tmp_fp_env->
lo_faults.
swa = 1;
02714
02715 }
else if (
fp_is_nan(tmp_fr2) ||
fp_is_nan(tmp_fr3)) {
02716
if (
fp_is_snan(tmp_fr2) ||
fp_is_snan(tmp_fr3)) {
02717 tmp_fp_env->
lo_flags.
v = 1;
02718
if (!tmp_fp_env->
controls.
vd) {
02719 tmp_fp_env->
lo_faults.
v = 1;
02720 }
02721 }
02722
if (
fp_is_nan(tmp_fr2)) {
02723 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr2)
02724 ?
fp_make_quiet_nan(tmp_fr2) : tmp_fr2;
02725 }
else if (
fp_is_nan(tmp_fr3)) {
02726 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr3)
02727 ?
fp_make_quiet_nan(tmp_fr3) : tmp_fr3;
02728 }
02729
02730
02731
02732 }
else if ( (
fp_is_inf(tmp_fr2) &&
fp_is_inf(tmp_fr3) )
02733 || (
fp_is_zero(tmp_fr2) &&
fp_is_zero(tmp_fr3) ) ) {
02734 tmp_fp_env->
lo_flags.
v = 1;
02735 tmp_reg_pair.
lo = FP_QNAN;
02736
if (!tmp_fp_env->
controls.
vd) {
02737 tmp_fp_env->
lo_faults.
v = 1;
02738 }
02739
02740
02741
02742
02743
02744 }
else if ( !
fp_is_inf(tmp_fr2) && !
fp_is_zero(tmp_fr2) &&
fp_is_zero(tmp_fr3) ) {
02745 tmp_fp_env->
lo_flags.
z = 1;
02746 tmp_reg_pair.
lo = FP_INFINITY;
02747 tmp_reg_pair.
lo.
sign = tmp_fr2.
sign ^ tmp_fr3.
sign;
02748
if (!tmp_fp_env->
controls.
zd) {
02749 tmp_fp_env->
lo_faults.
z = 1;
02750 }
02751
02752 }
else if (
fp_is_unorm(tmp_fr2) ||
fp_is_unorm(tmp_fr3)) {
02753 tmp_fp_env->
lo_flags.
d = 1;
02754
if (!tmp_fp_env->
controls.
dd) {
02755 tmp_fp_env->
lo_faults.
d = 1;
02756 }
02757 }
02758
02759
if ( !
fp_is_zero(tmp_fr2) &&
fp_is_finite(tmp_fr2)
02760 && !
fp_is_zero(tmp_fr3) &&
fp_is_finite(tmp_fr3) ) {
02761
02762 tmp_fr2 =
fp_normalize(tmp_fr2);
02763
02764
if (
fp_is_unorm(tmp_fr3) ) {
02765 limits_check->
lo_fr3 = 1;
02766 tmp_reg_pair.
lo = FP_INFINITY;
02767 tmp_reg_pair.
lo.
sign = tmp_fr3.
sign;
02768 tmp_fr3 =
fp_normalize(tmp_fr3);
02769
02770 }
else if ( tmp_fr3.
exponent >= (FP_REG_BIAS+FP_SGL_BIAS-2) ) {
02771 limits_check->
lo_fr3 = 1;
02772 tmp_reg_pair.
lo = FP_ZERO;
02773 tmp_reg_pair.
lo.
sign = tmp_fr3.
sign;
02774 }
02775
02776 estimated_exponent = (
EM_int_t)tmp_fr2.
exponent
02777 - (
EM_int_t)tmp_fr3.
exponent;
02778
02779
if ( (estimated_exponent >= (((
EM_int_t)(FP_SGL_BIAS))) )
02780 || (estimated_exponent <= (2-((
EM_int_t)FP_SGL_BIAS)) )
02781 || (tmp_fr2.
exponent <= (
ss_single_24+FP_REG_BIAS-FP_SGL_BIAS) )
02782 ) {
02783 limits_check->
lo_fr2_or_quot = 1;
02784 }
02785
02786 }
02787
02788
return (tmp_reg_pair);
02789 }
02790
02791
02792
02793
02794
EM_fp_reg_type
02795 frsqrta_exception_fault_check(
02796 EM_fp_reg_specifier f3,
02797 EM_opcode_sf_type sf,
02798
EM_tmp_fp_env_type *tmp_fp_env)
02799 {
02800
EM_fp_reg_type tmp_res, fr3;
02801
02802 fr3 =
FR[f3];
02803
fp_decode_environment(
pc_none, sf, tmp_fp_env );
02804
02805
if (
fp_software_assistance_required(ps,
op_frsqrta, fr3)) {
02806 tmp_fp_env->
em_faults.
swa = 1;
02807
return (FP_ZERO);
02808 }
02809
02810 tmp_res = FP_ZERO;
02811
02812
if (
fp_is_unsupported(fr3)) {
02813 tmp_fp_env->
flags.
v = 1;
02814 tmp_res = FP_QNAN;
02815
if (!tmp_fp_env->
controls.
vd) {
02816 tmp_fp_env->
em_faults.
v = 1;
02817 }
02818
02819 }
else if (
fp_is_nan(fr3)) {
02820
if(
fp_is_snan(fr3)){
02821 tmp_fp_env->
flags.
v = 1;
02822
if (!tmp_fp_env->
controls.
vd) {
02823 tmp_fp_env->
em_faults.
v = 1;
02824 }
02825 }
02826 tmp_res =
fp_is_snan(fr3)
02827 ?
fp_make_quiet_nan(fr3) : fr3;
02828
02829 }
else if (
fp_is_neg_inf(fr3)) {
02830 tmp_fp_env->
flags.
v = 1;
02831 tmp_res = FP_QNAN;
02832
if (!tmp_fp_env->
controls.
vd) {
02833 tmp_fp_env->
em_faults.
v = 1;
02834 }
02835
02836 }
else if (
fp_is_neg_non_zero(fr3) && !
fp_is_pseudo_zero(fr3)) {
02837 tmp_fp_env->
flags.
v = 1;
02838 tmp_res = FP_QNAN;
02839
if (!tmp_fp_env->
controls.
vd) {
02840 tmp_fp_env->
em_faults.
v = 1;
02841 }
02842
02843
02844 }
else if (
fp_is_unorm(fr3)) {
02845 tmp_fp_env->
flags.
d = 1;
02846
if( !tmp_fp_env->
controls.
dd) {
02847 tmp_fp_env->
em_faults.
d = 1;
02848 }
02849 }
02850
02851
02852
if( (
fp_is_pos_non_zero(fr3) && !
fp_is_pseudo_zero(fr3) )&&
fp_is_finite(fr3)) {
02853 fr3 =
fp_normalize(
fp_reg_read(fr3));
02854
if(fr3.
exponent <=
ss_double_extended_64) {
02855 tmp_fp_env->
em_faults.
swa = 1;
02856 }
02857 }
02858
02859
return (tmp_res);
02860 }
02861
02862
02863
02864
02865
EM_pair_fp_reg_type
02866 fprsqrta_exception_fault_check(
02867 EM_fp_reg_specifier f3,
02868 EM_opcode_sf_type sf,
02869
EM_tmp_fp_env_type *tmp_fp_env,
02870
EM_limits_check_fprsqrta *limits_check)
02871 {
02872
EM_pair_fp_reg_type tmp_reg_pair;
02873
EM_fp_reg_type tmp_fr3 =
FR[f3];
02874
02875
fp_decode_environment(
pc_simd, sf, tmp_fp_env );
02876
02877 tmp_reg_pair.
hi = FP_ZERO;
02878 tmp_reg_pair.
lo = FP_ZERO;
02879
02880
02881
02882
02883 tmp_fr3 =
fp_reg_read_hi(f3);
02884
if (
fp_software_assistance_required(ps,
op_fprsqrta, tmp_fr3)) {
02885 tmp_fp_env->
hi_faults.
swa = 1;
02886
02887 }
else if (
fp_is_nan(tmp_fr3)) {
02888
if (
fp_is_snan(tmp_fr3)) {
02889 tmp_fp_env->
hi_flags.
v = 1;
02890
if (!tmp_fp_env->
controls.
vd) {
02891 tmp_fp_env->
hi_faults.
v = 1;
02892 }
02893 }
02894 tmp_reg_pair.
hi =
fp_is_snan(tmp_fr3)
02895 ?
fp_make_quiet_nan(tmp_fr3) : tmp_fr3;
02896
02897 }
else if (
fp_is_neg_inf(tmp_fr3)) {
02898 tmp_fp_env->
hi_flags.
v = 1;
02899 tmp_reg_pair.
hi = FP_QNAN;
02900
if (!tmp_fp_env->
controls.
vd) {
02901 tmp_fp_env->
hi_faults.
v = 1;
02902 }
02903 }
else if (
fp_is_neg_non_zero(tmp_fr3)) {
02904 tmp_fp_env->
hi_flags.
v = 1;
02905 tmp_reg_pair.
hi = FP_QNAN;
02906
if (!tmp_fp_env->
controls.
vd) {
02907 tmp_fp_env->
hi_faults.
v = 1;
02908 }
02909
02910 }
else if (
fp_is_unorm(tmp_fr3)) {
02911 tmp_fp_env->
hi_flags.
d = 1;
02912
if (!tmp_fp_env->
controls.
dd) {
02913 tmp_fp_env->
hi_faults.
d = 1;
02914 }
02915
02916 }
02917
if(
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_finite(tmp_fr3)) {
02918 tmp_fr3 =
fp_normalize(tmp_fr3);
02919
if (tmp_fr3.
exponent <= (FP_REG_BIAS - FP_SGL_BIAS +
ss_single_24)) {
02920 limits_check->
hi = 1;
02921 }
else {
02922 limits_check->
hi = 0;
02923 }
02924 }
02925
02926
02927
02928
02929 tmp_fr3 =
fp_reg_read_lo(f3);
02930
02931
if (
fp_software_assistance_required(ps,
op_fprsqrta, tmp_fr3)) {
02932 tmp_fp_env->
lo_faults.
swa = 1;
02933
02934 }
else if (
fp_is_nan(tmp_fr3)) {
02935
if (
fp_is_snan(tmp_fr3)) {
02936 tmp_fp_env->
lo_flags.
v = 1;
02937
if (!tmp_fp_env->
controls.
vd) {
02938 tmp_fp_env->
lo_faults.
v = 1;
02939 }
02940 }
02941 tmp_reg_pair.
lo =
fp_is_snan(tmp_fr3)
02942 ?
fp_make_quiet_nan(tmp_fr3) : tmp_fr3;
02943
02944 }
else if (
fp_is_neg_inf(tmp_fr3)) {
02945 tmp_fp_env->
lo_flags.
v = 1;
02946 tmp_reg_pair.
lo = FP_QNAN;
02947
if (!tmp_fp_env->
controls.
vd) {
02948 tmp_fp_env->
lo_faults.
v = 1;
02949 }
02950 }
else if (
fp_is_neg_non_zero(tmp_fr3)) {
02951 tmp_fp_env->
lo_flags.
v = 1;
02952 tmp_reg_pair.
lo = FP_QNAN;
02953
if (!tmp_fp_env->
controls.
vd) {
02954 tmp_fp_env->
lo_faults.
v = 1;
02955 }
02956
02957 }
else if (
fp_is_unorm(tmp_fr3)) {
02958 tmp_fp_env->
lo_flags.
d = 1;
02959
if (!tmp_fp_env->
controls.
dd) {
02960 tmp_fp_env->
lo_faults.
d = 1;
02961 }
02962 }
02963
02964
if(
fp_is_pos_non_zero(tmp_fr3) &&
fp_is_finite(tmp_fr3)) {
02965 tmp_fr3 =
fp_normalize(tmp_fr3);
02966
if (tmp_fr3.
exponent <= (FP_REG_BIAS - FP_SGL_BIAS +
ss_single_24)) {
02967 limits_check->
lo = 1;
02968 }
else {
02969 limits_check->
lo = 0;
02970 }
02971 }
02972
02973
02974
return (tmp_reg_pair);
02975 }
02976
02977
02978
02979
INLINE EM_boolean_t
02980 fp_is_finite(
EM_fp_reg_type freg)
02981 {
02982
if (
fp_is_inf(freg) ||
fp_is_nan(freg) ||
fp_is_unsupported(freg) ) {
02983
return(0);
02984 }
else {
02985
return(1);
02986 }
02987 }
02988
02989
INLINE EM_boolean_t
02990 fp_is_inf(
EM_fp_reg_type freg)
02991 {
02992
if ( (freg.
exponent == FP_REG_EXP_ONES)
02993 &&(freg.
significand == U64_0x8000000000000000) ) {
02994
return(1);
02995 }
else {
02996
return(0);
02997 }
02998 }
02999
03000
INLINE EM_boolean_t
03001 fp_is_inf_dp(
EM_fp_dp_type tmp_res)
03002 {
03003
if ( (tmp_res.
exponent == FP_DP_EXP_ONES)
03004 &&
fp_U128_eq(tmp_res.
significand,
03005 U128_0x80000000000000000000000000000000) ) {
03006
return(1);
03007 }
else {
03008
return(0);
03009 }
03010 }
03011
03012
INLINE EM_boolean_t
03013 fp_is_nan(
EM_fp_reg_type freg)
03014 {
03015
if ( (freg.
exponent == FP_REG_EXP_ONES)
03016 && ((freg.
significand & U64_0x8000000000000000) != 0)
03017 && ((freg.
significand & U64_0x7FFFFFFFFFFFFFFF) != 0) ) {
03018
return(1);
03019 }
else {
03020
return(0);
03021 }
03022 }
03023
03024
INLINE EM_boolean_t
03025 fp_is_nan_dp(
EM_fp_dp_type tmp_res)
03026 {
03027
if ( (tmp_res.
exponent == FP_DP_EXP_ONES)
03028 &&
fp_U128_eq(U128_0x80000000000000000000000000000000,
03029
fp_U128_band(tmp_res.
significand,
03030 U128_0x80000000000000000000000000000000))
03031 && !
fp_U128_eq(U128_0,
03032
fp_U128_band(tmp_res.
significand,
03033 U128_0x7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))
03034 ) {
03035
return (1);
03036 }
else {
03037
return (0);
03038 }
03039 }
03040
03041
INLINE EM_boolean_t
03042 fp_is_natval(
EM_fp_reg_type freg)
03043 {
03044
if ( (freg.
sign == 0)
03045 && (freg.
exponent == 0x1FFFE)
03046 && (freg.
significand == U64_0) ) {
03047
return(1);
03048 }
else {
03049
return(0);
03050 }
03051 }
03052
03053
INLINE EM_boolean_t
03054 fp_is_neg_dp(
EM_fp_dp_type tmp_res)
03055 {
03056
if (tmp_res.
sign) {
03057
return(1);
03058 }
else {
03059
return(0);
03060 }
03061 }
03062
03063
INLINE EM_boolean_t
03064 fp_is_neg_inf(
EM_fp_reg_type freg)
03065 {
03066
if ( (freg.
sign == 1)
03067 && (freg.
exponent == FP_REG_EXP_ONES)
03068 && (freg.
significand == U64_0x8000000000000000) ) {
03069
return(1);
03070 }
else {
03071
return(0);
03072 }
03073 }
03074
03075
INLINE EM_boolean_t
03076 fp_is_neg_non_zero(
EM_fp_reg_type freg)
03077 {
03078
if ( (freg.
sign == 1) && !
fp_is_zero(freg) ) {
03079
return(1);
03080 }
else {
03081
return(0);
03082 }
03083 }
03084
03085
INLINE EM_boolean_t
03086 fp_is_normal(
EM_fp_reg_type freg)
03087 {
03088
if ( (freg.
exponent != 0)
03089 && (freg.
exponent != FP_REG_EXP_ONES)
03090 && ((freg.
significand & U64_0x8000000000000000) != 0) ) {
03091
return(1);
03092 }
else {
03093
return(0);
03094 }
03095 }
03096
03097
INLINE EM_boolean_t
03098 fp_is_normal_dp(
EM_fp_dp_type tmp_res)
03099 {
03100
if ( (tmp_res.
exponent != 0)
03101 && (tmp_res.
exponent != FP_DP_EXP_ONES)
03102 &&
fp_U128_eq(U128_0x80000000000000000000000000000000,
03103
fp_U128_band(tmp_res.
significand,
03104 U128_0x80000000000000000000000000000000))
03105 ) {
03106
return(1);
03107 }
else {
03108
return(0);
03109 }
03110 }
03111
03112
INLINE EM_boolean_t
03113 fp_is_pos_dp(
EM_fp_dp_type tmp_res)
03114 {
03115
if (!tmp_res.
sign) {
03116
return(1);
03117 }
else {
03118
return(0);
03119 }
03120 }
03121
03122
INLINE EM_boolean_t
03123 fp_is_pos_inf(
EM_fp_reg_type freg)
03124 {
03125
if ( (freg.
sign == 0)
03126 && (freg.
exponent == FP_REG_EXP_ONES)
03127 && (freg.
significand == U64_0x8000000000000000) ) {
03128
return(1);
03129 }
else {
03130
return(0);
03131 }
03132 }
03133
03134
INLINE EM_boolean_t
03135 fp_is_pos_non_zero(
EM_fp_reg_type freg)
03136 {
03137
if ( (freg.
sign == 0) && !
fp_is_zero(freg) ) {
03138
return(1);
03139 }
else {
03140
return(0);
03141 }
03142 }
03143
03144
INLINE EM_boolean_t
03145 fp_is_pseudo_zero(
EM_fp_reg_type freg)
03146 {
03147
if ( (freg.
exponent != 0)
03148 && (freg.
exponent != FP_REG_EXP_ONES)
03149 && (freg.
significand == U64_0 && !
fp_is_natval (freg)) ) {
03150
return(1);
03151 }
else {
03152
return(0);
03153 }
03154 }
03155
03156
INLINE EM_boolean_t
03157 fp_is_qnan(
EM_fp_reg_type freg)
03158 {
03159
if ( (freg.
exponent == FP_REG_EXP_ONES)
03160 &&((freg.
significand & U64_0xC000000000000000) == U64_0xC000000000000000) ) {
03161
return(1);
03162 }
else {
03163
return(0);
03164 }
03165 }
03166
03167
INLINE EM_boolean_t
03168 fp_is_snan(
EM_fp_reg_type freg)
03169 {
03170
if ( (freg.
exponent == FP_REG_EXP_ONES)
03171 &&((freg.
significand & U64_0xC000000000000000) == U64_0x8000000000000000)
03172 &&((freg.
significand & U64_0x3FFFFFFFFFFFFFFF) != 0) ) {
03173
return(1);
03174 }
else {
03175
return(0);
03176 }
03177 }
03178
03179
INLINE EM_boolean_t
03180 fp_is_unorm(
EM_fp_reg_type freg)
03181 {
03182
if ( ( (freg.
exponent != 0)
03183 && (freg.
exponent != FP_REG_EXP_ONES)
03184 &&((freg.
significand & U64_0x8000000000000000) == 0) )
03185
03186 || ( (freg.
exponent == 0) && (freg.
significand != 0) ) ) {
03187
return(1);
03188 }
else {
03189
return(0);
03190 }
03191 }
03192
03193
INLINE EM_boolean_t
03194 fp_is_unorm_dp(
EM_fp_dp_type tmp_res)
03195 {
03196
if ( (tmp_res.
exponent != 0)
03197 && (tmp_res.
exponent != FP_DP_EXP_ONES)
03198 &&((tmp_res.
significand.
hi & U64_0x8000000000000000) == 0) ) {
03199
return(1);
03200 }
else {
03201
return(0);
03202 }
03203 }
03204
03205
INLINE EM_boolean_t
03206 fp_is_unsupported(
EM_fp_reg_type freg)
03207 {
03208
if (
fp_is_natval(freg) ||
fp_is_nan(freg) ||
fp_is_inf(freg)
03209 ||
fp_is_normal(freg) ||
fp_is_unorm(freg) ||
fp_is_zero(freg) ) {
03210
return(0);
03211 }
else {
03212
return(1);
03213 }
03214 }
03215
03216
INLINE EM_boolean_t
03217 fp_is_unsupported_dp(
EM_fp_dp_type tmp_res)
03218 {
03219
if (
fp_is_nan_dp(tmp_res) ||
fp_is_inf_dp(tmp_res)
03220 ||
fp_is_normal_dp(tmp_res) ||
fp_is_unorm_dp(tmp_res)
03221 ||
fp_is_zero_dp(tmp_res) ) {
03222
return(0);
03223 }
else {
03224
return(1);
03225 }
03226 }
03227
03228
INLINE EM_boolean_t
03229 fp_is_zero(
EM_fp_reg_type freg)
03230 {
03231
if ( (freg.
exponent == 0) && (freg.
significand == U64_0) ) {
03232
return(1);
03233 }
else {
03234
return(0);
03235 }
03236 }
03237
03238
INLINE EM_boolean_t
03239 fp_is_zero_dp(
EM_fp_dp_type tmp_res)
03240 {
03241
if ( (tmp_res.
exponent == 0) &&
fp_U128_eq(tmp_res.
significand, U128_0) ) {
03242
return(1);
03243 }
else {
03244
return(0);
03245 }
03246 }
03247
03248
EM_int_t
03249 fp82_fp_U64_lead0(EM_uint64_t value)
03250 {
03251
EM_int_t tmp_i, offset=0;
03252
EM_uint64_t tmp_mask;
03253
03254
if( value == U64_0)
03255
return(64);
03256
03257 tmp_mask = U64_0x8000000000000000;
03258
03259
if( (value & U64_0xFFFFFFFF00000000) != U64_0) {
03260
03261
if( (value & U64_0xFFFF000000000000) != U64_0) {
03262
03263
if( (value & U64_0xFF00000000000000) != U64_0) {
03264
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03265
if ( (value & tmp_mask) != U64_0 ) {
03266
return(tmp_i);
03267 }
03268 }
03269 }
03270
else {
03271 value <<= 8;
03272 offset += 8;
03273
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03274
if ( (value & tmp_mask) != U64_0 ) {
03275
return(tmp_i + offset);
03276 }
03277 }
03278 }
03279 }
03280
else {
03281 value <<= 16;
03282 offset += 16;
03283
if( (value & U64_0xFF00000000000000) != U64_0) {
03284
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03285
if ( (value & tmp_mask) != U64_0 ) {
03286
return(tmp_i + offset);
03287 }
03288 }
03289 }
03290
else {
03291 value <<= 8;
03292 offset += 8;
03293
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03294
if ( (value & tmp_mask) != U64_0 ) {
03295
return(tmp_i + offset);
03296 }
03297 }
03298 }
03299 }
03300 }
03301
else {
03302 value <<= 32;
03303 offset += 32;
03304
if( (value & U64_0xFFFF000000000000) != U64_0) {
03305
03306
if( (value & U64_0xFF00000000000000) != U64_0) {
03307
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03308
if ( (value & tmp_mask) != U64_0 ) {
03309
return(tmp_i + offset);
03310 }
03311 }
03312 }
03313
else {
03314 value <<= 8;
03315 offset += 8;
03316
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03317
if ( (value & tmp_mask) != U64_0 ) {
03318
return(tmp_i + offset);
03319 }
03320 }
03321 }
03322 }
03323
else {
03324 value <<= 16;
03325 offset += 16;
03326
if( (value & U64_0xFF00000000000000) != U64_0) {
03327
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03328
if ( (value & tmp_mask) != U64_0 ) {
03329
return(tmp_i + offset);
03330 }
03331 }
03332 }
03333
else {
03334 value <<= 8;
03335 offset += 8;
03336
for (tmp_i=0; tmp_i<8; tmp_i++, tmp_mask>>=1) {
03337
if ( (value & tmp_mask) != U64_0 ) {
03338
return(tmp_i + offset);
03339 }
03340 }
03341 }
03342 }
03343 }
03344
03345
return(64);
03346
03347 }
03348
03349
EM_int_t
03350 fp_U128_lead0(
EM_uint128_t value)
03351 {
03352
EM_int_t tmp_i;
03353
03354 tmp_i =
fp_U64_lead0(value.
hi);
03355
if (tmp_i == 64) {
03356 tmp_i +=
fp_U64_lead0(value.
lo);
03357 }
03358
return(tmp_i);
03359 }
03360
03361
EM_int_t
03362 fp82_fp_U256_lead0(
EM_uint256_t value)
03363 {
03364
EM_int_t tmp_i;
03365
03366 tmp_i =
fp_U64_lead0(value.
hh);
03367
if (tmp_i == 64) {
03368 tmp_i +=
fp_U64_lead0(value.
hl);
03369
if (tmp_i == 128) {
03370 tmp_i +=
fp_U64_lead0(value.
lh);
03371
if (tmp_i == 192) {
03372 tmp_i +=
fp_U64_lead0(value.
ll);
03373 }
03374 }
03375 }
03376
return(tmp_i);
03377 }
03378
03379
03380
03381
03382
EM_fp_reg_type
03383 fp_mem_to_fr_format(
03384
EM_memory_type mem,
03385 EM_uint_t size,
03386 EM_uint_t integer_form)
03387 {
03388
03389
03390
03391
03392
03393
03394
EM_fp_reg_type tmp_freg;
03395
EM_uint64_t tmp_significand, tmp_significand_hi, tmp_significand_lo;
03396
03397
switch (size) {
03398
case 4:
03399 tmp_freg.
sign = mem.
fp_single.
sign;
03400
if ( (mem.
fp_single.
exponent == 0)
03401 && (mem.
fp_single.
significand == 0) ) {
03402 tmp_freg.
exponent = 0;
03403 }
else if (mem.
fp_single.
exponent == 0) {
03404 tmp_freg.
exponent = (
EM_uint_t)(FP_REG_BIAS - FP_SGL_BIAS + 1);
03405 }
else if (mem.
fp_single.
exponent == FP_SGL_EXP_ONES) {
03406 tmp_freg.
exponent = FP_REG_EXP_ONES;
03407 }
else {
03408 tmp_freg.
exponent = (
EM_uint_t)
03409 (((
EM_int_t)mem.
fp_single.
exponent)
03410 - FP_SGL_BIAS + FP_REG_BIAS);
03411 }
03412 tmp_freg.
significand =
03413 (((
EM_uint64_t)mem.
fp_single.
significand)<<40)
03414
#ifdef HPC_BUGS
03415
| (((mem.
fp_single.
exponent != U64_0)?U64_1:U64_0)<<63);
03416
#else
03417
| (((mem.
fp_single.
exponent != 0)?U64_1:U64_0)<<63);
03418
#endif
03419
03420
break;
03421
03422
case 8:
03423
if (integer_form) {
03424 tmp_freg.
sign = 0;
03425 tmp_freg.
significand = mem.
uint_64.
uvalue;
03426 tmp_freg.
exponent = FP_INTEGER_EXP;
03427 }
else {
03428 tmp_freg.
sign = mem.
fp_double.
sign;
03429
if ( (mem.
fp_double.
exponent == 0)
03430 && (mem.
fp_double.
significand_hi == 0)
03431 && (mem.
fp_double.
significand_lo == 0) ){
03432 tmp_freg.
exponent = 0;
03433 }
else if (mem.
fp_double.
exponent == 0) {
03434 tmp_freg.
exponent = (
EM_uint_t)(FP_REG_BIAS - FP_DBL_BIAS + 1);
03435 }
else if (mem.
fp_double.
exponent == FP_DBL_EXP_ONES) {
03436 tmp_freg.
exponent = FP_REG_EXP_ONES;
03437 }
else {
03438 tmp_freg.
exponent = (
EM_uint_t)
03439 (((
EM_int_t)mem.
fp_double.
exponent)
03440 - FP_DBL_BIAS + FP_REG_BIAS);
03441 }
03442 tmp_significand_lo = ((
EM_uint64_t)(mem.
fp_double.
significand_lo)) ;
03443 tmp_significand_hi = (((
EM_uint64_t)(mem.
fp_double.
significand_hi)) << 32);
03444 tmp_significand = tmp_significand_lo | tmp_significand_hi;
03445
03446 tmp_freg.
significand =
03447 (tmp_significand<<11)
03448
#ifdef HPC_BUGS
03449
| (((mem.
fp_double.
exponent != U64_0)?U64_1:U64_0)<<63);
03450
#else
03451
| (((mem.
fp_double.
exponent != 0)?U64_1:U64_0)<<63);
03452
#endif
03453
}
03454
break;
03455
03456
case 10:
03457 tmp_freg.
sign = mem.
fp_double_extended.
sign;
03458
if (mem.
fp_double_extended.
exponent == 0) {
03459
03460 tmp_freg.
exponent = 0;
03461 }
else if (mem.
fp_double_extended.
exponent == FP_EXT_EXP_ONES) {
03462
03463 tmp_freg.
exponent = FP_REG_EXP_ONES;
03464 }
else {
03465 tmp_freg.
exponent = (
EM_uint_t)
03466 (((
EM_int_t)mem.
fp_double_extended.
exponent)
03467 - FP_EXT_BIAS + FP_REG_BIAS);
03468 }
03469 memcpy(&tmp_freg.
significand,
03470 mem.
fp_double_extended.
significand, 8);
03471
break;
03472
03473
case 16:
03474 tmp_freg.
sign = mem.
fp_spill_fill.
sign;
03475 tmp_freg.
exponent = mem.
fp_spill_fill.
exponent;
03476 tmp_freg.
significand = mem.
fp_spill_fill.
significand;
03477
break;
03478 }
03479
return (tmp_freg);
03480 }
03481
03482
03483
INLINE EM_fp_reg_type
03484 fp_make_quiet_nan(
EM_fp_reg_type freg)
03485 {
03486 freg.
significand |= U64_0x4000000000000000;
03487
return (freg);
03488 }
03489
03490
03491
03492
EM_boolean_t
03493 fp82_fp_raise_fault(
EM_tmp_fp_env_type tmp_fp_env)
03494 {
03495
if(tmp_fp_env.
simd == 1) {
03496
if (tmp_fp_env.
lo_faults.
swa || tmp_fp_env.
lo_faults.
v
03497 || tmp_fp_env.
lo_faults.
d || tmp_fp_env.
lo_faults.
z
03498
03499 || tmp_fp_env.
hi_faults.
swa || tmp_fp_env.
hi_faults.
v
03500 || tmp_fp_env.
hi_faults.
d || tmp_fp_env.
hi_faults.
z )
03501
03502
return(1);
03503 }
else if ( tmp_fp_env.
em_faults.
swa || tmp_fp_env.
em_faults.
v
03504 || tmp_fp_env.
em_faults.
d || tmp_fp_env.
em_faults.
z )
03505
return (1);
03506
return (0);
03507 }
03508
03509
03510
EM_boolean_t
03511 fp82_fp_raise_traps(
EM_tmp_fp_env_type tmp_fp_env)
03512 {
03513
if(tmp_fp_env.
simd == 1) {
03514
if (tmp_fp_env.
hi_traps.
o || tmp_fp_env.
hi_traps.
un || tmp_fp_env.
hi_traps.
i
03515 || tmp_fp_env.
lo_traps.
o || tmp_fp_env.
lo_traps.
un || tmp_fp_env.
lo_traps.
i)
03516
return (1);
03517 }
else if (tmp_fp_env.
em_traps.
o || tmp_fp_env.
em_traps.
un || tmp_fp_env.
em_traps.
i)
03518
return (1);
03519
return (0);
03520 }
03521
03522
03523
INLINE EM_fp_reg_type
03524 fp_reg_read(
EM_fp_reg_type freg)
03525 {
03526
EM_fp_reg_type tmp_freg;
03527 tmp_freg = freg;
03528
03529
if ((tmp_freg.
exponent == 0) && (tmp_freg.
significand != U64_0))
03530 tmp_freg.
exponent=0x0C001;
03531
return (tmp_freg);
03532 }
03533
03534
03535
03536
03537
03538
03539
INLINE void
03540 fp_update_fpsr(
03541 EM_opcode_sf_type sf,
03542
EM_tmp_fp_env_type tmp_fp_env )
03543 {
03544
if (sf ==
sf_none) {
03545
return;
03546 }
03547
else if (sf ==
sfS0) {
03548
03549
03550
03551
03552
if(tmp_fp_env.
simd == 1) {
03553
03554
03555
if (tmp_fp_env.
hi_flags.
v || tmp_fp_env.
lo_flags.
v) {
03556
SET_STATUS_FLAG(
FPSR.sf0_flags_v);
03557 }
03558
if (tmp_fp_env.
hi_flags.
d || tmp_fp_env.
lo_flags.
d) {
03559
SET_STATUS_FLAG(
FPSR.sf0_flags_d);
03560 }
03561
if (tmp_fp_env.
hi_flags.
z || tmp_fp_env.
lo_flags.
z) {
03562
SET_STATUS_FLAG(
FPSR.sf0_flags_z);
03563 }
03564
03565
03566
03567
if (tmp_fp_env.
hi_flags.
o || tmp_fp_env.
lo_flags.
o) {
03568
SET_STATUS_FLAG(
FPSR.sf0_flags_o);
03569 }
03570
if (tmp_fp_env.
hi_flags.
un || tmp_fp_env.
lo_flags.
un) {
03571
SET_STATUS_FLAG(
FPSR.sf0_flags_u);
03572 }
03573
if (tmp_fp_env.
hi_flags.
i || tmp_fp_env.
lo_flags.
i) {
03574
SET_STATUS_FLAG(
FPSR.sf0_flags_i);
03575 }
03576 }
03577
03578
else {
03579
03580
03581
if (tmp_fp_env.
flags.
v) {
03582
SET_STATUS_FLAG(
FPSR.sf0_flags_v);
03583 }
03584
if (tmp_fp_env.
flags.
d) {
03585
03586
SET_STATUS_FLAG(
FPSR.sf0_flags_d);
03587 }
03588
if (tmp_fp_env.
flags.
z) {
03589
SET_STATUS_FLAG(
FPSR.sf0_flags_z);
03590 }
03591
03592
03593
03594
if (tmp_fp_env.
flags.
o) {
03595
SET_STATUS_FLAG(
FPSR.sf0_flags_o);
03596
if ( tmp_fp_env.
flags.
i) {
03597
SET_STATUS_FLAG(
FPSR.sf0_flags_i);
03598 }
03599 }
03600
else if (tmp_fp_env.
flags.
un) {
03601
SET_STATUS_FLAG(
FPSR.sf0_flags_u);
03602
if ( tmp_fp_env.
flags.
i ) {
03603
SET_STATUS_FLAG(
FPSR.sf0_flags_i);
03604 }
03605 }
03606
else if (tmp_fp_env.
flags.
i) {
03607
SET_STATUS_FLAG(
FPSR.sf0_flags_i);
03608 }
03609 }
03610 }
03611
03612
03613
03614
03615
else if (sf ==
sfS1) {
03616
if(tmp_fp_env.
simd == 1) {
03617
03618
03619
03620
if (tmp_fp_env.
hi_flags.
v || tmp_fp_env.
lo_flags.
v) {
03621
SET_STATUS_FLAG(
FPSR.sf1_flags_v);
03622 }
03623
if (tmp_fp_env.
hi_flags.
d || tmp_fp_env.
lo_flags.
d) {
03624
SET_STATUS_FLAG(
FPSR.sf1_flags_d);
03625 }
03626
if (tmp_fp_env.
hi_flags.
z || tmp_fp_env.
lo_flags.
z) {
03627
SET_STATUS_FLAG(
FPSR.sf1_flags_z);
03628 }
03629
03630
03631
03632
if (tmp_fp_env.
hi_flags.
o || tmp_fp_env.
lo_flags.
o) {
03633
SET_STATUS_FLAG(
FPSR.sf1_flags_o);
03634 }
03635
if (tmp_fp_env.
hi_flags.
un || tmp_fp_env.
lo_flags.
un) {
03636
SET_STATUS_FLAG(
FPSR.sf1_flags_u);
03637 }
03638
if (tmp_fp_env.
hi_flags.
i || tmp_fp_env.
lo_flags.
i) {
03639
SET_STATUS_FLAG(
FPSR.sf1_flags_i);
03640 }
03641 }
03642
03643
else {
03644
03645
03646
03647
if (tmp_fp_env.
flags.
v ) {
03648
SET_STATUS_FLAG(
FPSR.sf1_flags_v);
03649 }
03650
if (tmp_fp_env.
flags.
d ) {
03651
SET_STATUS_FLAG(
FPSR.sf1_flags_d);
03652 }
03653
if (tmp_fp_env.
flags.
z ) {
03654
SET_STATUS_FLAG(
FPSR.sf1_flags_z);
03655 }
03656
03657
03658
03659
if ( tmp_fp_env.
flags.
o ) {
03660
SET_STATUS_FLAG(
FPSR.sf1_flags_o);
03661
if ( tmp_fp_env.
flags.
i ) {
03662
SET_STATUS_FLAG(
FPSR.sf1_flags_i);
03663 }
03664 }
03665
else if (tmp_fp_env.
flags.
un ) {
03666
SET_STATUS_FLAG(
FPSR.sf1_flags_u);
03667
if ( tmp_fp_env.
flags.
i ) {
03668
SET_STATUS_FLAG(
FPSR.sf1_flags_i);
03669 }
03670 }
03671
else if (tmp_fp_env.
flags.
i ) {
03672
SET_STATUS_FLAG(
FPSR.sf1_flags_i);
03673 }
03674 }
03675 }
03676
03677
03678
03679
03680
else if (sf ==
sfS2) {
03681
if(tmp_fp_env.
simd == 1) {
03682
03683
03684
03685
if (tmp_fp_env.
hi_flags.
v || tmp_fp_env.
lo_flags.
v) {
03686
SET_STATUS_FLAG(
FPSR.sf2_flags_v);
03687 }
03688
if (tmp_fp_env.
hi_flags.
d || tmp_fp_env.
lo_flags.
d) {
03689
SET_STATUS_FLAG(
FPSR.sf2_flags_d);
03690 }
03691
if (tmp_fp_env.
hi_flags.
z || tmp_fp_env.
lo_flags.
z) {
03692
SET_STATUS_FLAG(
FPSR.sf2_flags_z);
03693 }
03694
03695
03696
03697
if (tmp_fp_env.
hi_flags.
o || tmp_fp_env.
lo_flags.
o) {
03698
SET_STATUS_FLAG(
FPSR.sf2_flags_o);
03699 }
03700
if (tmp_fp_env.
hi_flags.
un || tmp_fp_env.
lo_flags.
un) {
03701
SET_STATUS_FLAG(
FPSR.sf2_flags_u);
03702 }
03703
if (tmp_fp_env.
hi_flags.
i || tmp_fp_env.
lo_flags.
i) {
03704
SET_STATUS_FLAG(
FPSR.sf2_flags_i);
03705 }
03706 }
03707
03708
else {
03709
03710
03711
03712
if (tmp_fp_env.
flags.
v ) {
03713
SET_STATUS_FLAG(
FPSR.sf2_flags_v);
03714 }
03715
if (tmp_fp_env.
flags.
d ) {
03716
SET_STATUS_FLAG(
FPSR.sf2_flags_d);
03717 }
03718
if (tmp_fp_env.
flags.
z ) {
03719
SET_STATUS_FLAG(
FPSR.sf2_flags_z);
03720 }
03721
03722
03723
03724
if ( tmp_fp_env.
flags.
o ) {
03725
SET_STATUS_FLAG(
FPSR.sf2_flags_o);
03726
if ( tmp_fp_env.
flags.
i ) {
03727
SET_STATUS_FLAG(
FPSR.sf2_flags_i);
03728 }
03729 }
03730
else if (tmp_fp_env.
flags.
un ) {
03731
SET_STATUS_FLAG(
FPSR.sf2_flags_u);
03732
if ( tmp_fp_env.
flags.
i ) {
03733
SET_STATUS_FLAG(
FPSR.sf2_flags_i);
03734 }
03735 }
03736
else if (tmp_fp_env.
flags.
i ) {
03737
SET_STATUS_FLAG(
FPSR.sf2_flags_i);
03738 }
03739 }
03740 }
03741
03742
03743
03744
03745
else if (sf ==
sfS3) {
03746
if(tmp_fp_env.
simd == 1) {
03747
03748
03749
03750
if (tmp_fp_env.
hi_flags.
v || tmp_fp_env.
lo_flags.
v) {
03751
SET_STATUS_FLAG(
FPSR.sf3_flags_v);
03752 }
03753
if (tmp_fp_env.
hi_flags.
d || tmp_fp_env.
lo_flags.
d) {
03754
SET_STATUS_FLAG(
FPSR.sf3_flags_d);
03755 }
03756
if (tmp_fp_env.
hi_flags.
z || tmp_fp_env.
lo_flags.
z) {
03757
SET_STATUS_FLAG(
FPSR.sf3_flags_z);
03758 }
03759
03760
03761
03762
if (tmp_fp_env.
hi_flags.
o || tmp_fp_env.
lo_flags.
o) {
03763
SET_STATUS_FLAG(
FPSR.sf3_flags_o);
03764 }
03765
if (tmp_fp_env.
hi_flags.
un || tmp_fp_env.
lo_flags.
un) {
03766
SET_STATUS_FLAG(
FPSR.sf3_flags_u);
03767 }
03768
if (tmp_fp_env.
hi_flags.
i || tmp_fp_env.
lo_flags.
i) {
03769
SET_STATUS_FLAG(
FPSR.sf3_flags_i);
03770 }
03771 }
03772
03773
else {
03774
03775
03776
03777
if (tmp_fp_env.
flags.
v ) {
03778
SET_STATUS_FLAG(
FPSR.sf3_flags_v);
03779 }
03780
if (tmp_fp_env.
flags.
d ) {
03781
SET_STATUS_FLAG(
FPSR.sf3_flags_d);
03782 }
03783
if (tmp_fp_env.
flags.
z ) {
03784
SET_STATUS_FLAG(
FPSR.sf3_flags_z);
03785 }
03786
03787
03788
03789
if ( tmp_fp_env.
flags.
o ) {
03790
SET_STATUS_FLAG(
FPSR.sf3_flags_o);
03791
if ( tmp_fp_env.
flags.
i ) {
03792
SET_STATUS_FLAG(
FPSR.sf3_flags_i);
03793 }
03794 }
03795
else if (tmp_fp_env.
flags.
un ) {
03796
SET_STATUS_FLAG(
FPSR.sf3_flags_u);
03797
if ( tmp_fp_env.
flags.
i ) {
03798
SET_STATUS_FLAG(
FPSR.sf3_flags_i);
03799 }
03800 }
03801
else if (tmp_fp_env.
flags.
i ) {
03802
SET_STATUS_FLAG(
FPSR.sf3_flags_i);
03803 }
03804 }
03805 }
03806 }
03807
03808
INLINE void
03809 fp_update_psr(EM_uint_t dest_freg)
03810 {
03811
EM_uint_t disabled_limit = 31;
03812
03813
if ( (dest_freg >= 2) && (dest_freg <= disabled_limit) ){
03814
SET_STATUS_FLAG(
PSR.mfl);
03815 }
03816
else if ( (dest_freg > disabled_limit) ) {
03817
SET_STATUS_FLAG(
PSR.mfh);
03818 }
03819 }
03820
03821
03822
03823
03824
03825
03826
EM_boolean_t
03827 fp82_fp_U128_eq(
EM_uint128_t value1,
EM_uint128_t value2)
03828 {
03829
if ( (value1.
hi == value2.
hi)
03830 && (value1.
lo == value2.
lo) )
03831
return (1);
03832
else
03833
return (0);
03834 }
03835
03836
static INLINE EM_boolean_t
03837 fp_U128_ge(
EM_uint128_t value1,
EM_uint128_t value2)
03838 {
03839
if (value1.
hi > value2.
hi)
03840
return (1);
03841
else if ( (value1.
hi == value2.
hi)
03842 && (value1.
lo >= value2.
lo) )
03843
return (1);
03844
else
03845
return (0);
03846 }
03847
03848
static INLINE EM_boolean_t
03849 fp_U128_gt(
EM_uint128_t value1,
EM_uint128_t value2)
03850 {
03851
if (value1.
hi > value2.
hi)
03852
return (1);
03853
else if ( (value1.
hi == value2.
hi)
03854 && (value1.
lo > value2.
lo) )
03855
return (1);
03856
else
03857
return (0);
03858 }
03859
03860
static INLINE EM_boolean_t
03861 fp_U128_le(
EM_uint128_t value1,
EM_uint128_t value2)
03862 {
03863
if (value1.
hi < value2.
hi)
03864
return (1);
03865
else if ( (value1.
hi == value2.
hi)
03866 && (value1.
lo <= value2.
lo) )
03867
return (1);
03868
else
03869
return (0);
03870 }
03871
03872
EM_boolean_t
03873 fp82_fp_U128_lt(
EM_uint128_t value1,
EM_uint128_t value2)
03874 {
03875
if (value1.
hi < value2.
hi)
03876
return (1);
03877
else if ( (value1.
hi == value2.
hi)
03878 && (value1.
lo < value2.
lo) )
03879
return (1);
03880
else
03881
return (0);
03882 }
03883
03884
EM_uint128_t
03885 fp82_fp_U128_lsh(
EM_uint128_t value, EM_uint_t count)
03886 {
03887
EM_uint128_t tmp;
03888
03889
if (count == 0) {
03890
return(value);
03891 }
else if (count >= 128) {
03892
return (U128_0);
03893
03894 }
else if (count > 64) {
03895 tmp.
lo = U64_0;
03896 tmp.
hi = (value.
lo<<(count-64));
03897
return (tmp);
03898 }
else if (count == 64) {
03899 tmp.
lo = U64_0;
03900 tmp.
hi = value.
lo;
03901
return (tmp);
03902 }
else if (count > 0) {
03903 tmp.
lo = (value.
lo<<count);
03904 tmp.
hi = (value.
hi<<count) | (value.
lo>>(64-count)) ;
03905
return (tmp);
03906 }
03907
return(value);
03908 }
03909
03910
EM_uint128_t
03911 fp82_fp_U128_rsh(
EM_uint128_t value, EM_uint_t count)
03912 {
03913
EM_uint128_t tmp;
03914
03915
if (count == 0) {
03916
return (value);
03917 }
else if (count >= 128) {
03918
return (U128_0);
03919
03920 }
else if (count > 64) {
03921 tmp.
lo = (value.
hi>>(count-64));
03922 tmp.
hi = U64_0;
03923
return (tmp);
03924 }
else if (count == 64) {
03925 tmp.
lo = value.
hi;
03926 tmp.
hi = U64_0;
03927
return (tmp);
03928 }
else if (count > 0) {
03929 tmp.
lo = (value.
lo>>count) | (value.
hi<<(64-count));
03930 tmp.
hi = (value.
hi>>count);
03931
return (tmp);
03932 }
03933
return(U128_0);
03934 }
03935
03936
EM_uint128_t
03937 fp82_fp_U64_x_U64_to_U128(EM_uint64_t value1, EM_uint64_t value2)
03938 {
03939
EM_uint128_t tmp_res;
03940
EM_uint64_t r0, s0, t0;
03941
EM_uint64_t r1, s1, t1;
03942
03943 s0 = (value1<<32)>>32;
03944 s1 = (value1>>32);
03945
03946 t0 = (value2<<32)>>32;
03947 t1 = (value2>>32);
03948
03949
#ifdef HPC_BUGS
03950
s0 = ((
EM_uint64_t)( ( ( ((
EM_int64_t)s0) << 32 ) >> 32 ) ));
03951 s1 = ((
EM_uint64_t)( ( ( ((
EM_int64_t)s1) << 32 ) >> 32 ) ));
03952 t0 = ((
EM_uint64_t)( ( ( ((
EM_int64_t)t0) << 32 ) >> 32 ) ));
03953 t1 = ((
EM_uint64_t)( ( ( ((
EM_int64_t)t1) << 32 ) >> 32 ) ));
03954
#endif
03955
03956 tmp_res.
lo = s0 * t0;
03957
03958
#ifdef HPC_BUGS
03959
if(s0 & U64_0x0000000080000000)
03960 tmp_res.
lo += t0<<32;
03961
if(t0 & U64_0x0000000080000000)
03962 tmp_res.
lo += s0<<32;
03963
#endif
03964
03965
03966 r0 = s0 * t1;
03967
03968
#ifdef HPC_BUGS
03969
if(s0 & U64_0x0000000080000000)
03970 r0 += t1<<32;
03971
if(t1 & U64_0x0000000080000000)
03972 r0 += s0<<32;
03973
#endif
03974
03975
03976 r1 = s1 * t0;
03977
03978
#ifdef HPC_BUGS
03979
if(s1 & U64_0x0000000080000000)
03980 r1 += t0<<32;
03981
if(t0 & U64_0x0000000080000000)
03982 r1 += s1<<32;
03983
#endif
03984
03985
03986 tmp_res.
hi = s1 * t1;
03987
03988
#ifdef HPC_BUGS
03989
if(s1 & U64_0x0000000080000000)
03990 tmp_res.
hi += t1<<32;
03991
if(t1 & U64_0x0000000080000000)
03992 tmp_res.
hi += s1<<32;
03993
#endif
03994
03995
03996
if ( (tmp_res.
lo + (r0<<32)) < tmp_res.
lo)
03997 tmp_res.
hi++;
03998
03999 tmp_res.
lo += (r0<<32);
04000
04001
if ( (tmp_res.
lo + (r1<<32)) < tmp_res.
lo)
04002 tmp_res.
hi++;
04003
04004 tmp_res.
lo += (r1<<32);
04005 tmp_res.
hi += (r0>>32);
04006 tmp_res.
hi += (r1>>32);
04007
04008
return (tmp_res);
04009 }
04010
04011
INLINE EM_uint128_t
04012 fp_I64_x_I64_to_I128(EM_uint64_t value1, EM_uint64_t value2)
04013 {
04014
EM_uint128_t tmp_res;
04015
EM_uint128_t scratch;
04016
04017 tmp_res =
fp_U64_x_U64_to_U128(value1, value2);
04018
04019
if (value1 & U64_0x8000000000000000) {
04020 scratch =
fp_U64_to_U128(value2);
04021 scratch =
fp_U128_lsh(scratch,64);
04022 scratch =
fp_U128_neg(scratch);
04023 tmp_res =
fp_U128_add(scratch, tmp_res);
04024 }
04025
04026
if (value2 & U64_0x8000000000000000) {
04027 scratch =
fp_U64_to_U128(value1);
04028 scratch =
fp_U128_lsh(scratch,64);
04029 scratch =
fp_U128_neg(scratch);
04030 tmp_res =
fp_U128_add(scratch, tmp_res);
04031 }
04032
04033
return (tmp_res);
04034 }
04035
04036
EM_uint128_t
04037 fp82_fp_U128_inc(
EM_uint128_t value)
04038 {
04039
EM_uint128_t tmp;
04040
04041 tmp.
lo = value.
lo + 1;
04042 tmp.
hi = value.
hi + (tmp.
lo < value.
lo);
04043
04044
return (tmp);
04045 }
04046
04047
static INLINE EM_uint128_t
04048 fp_U128_neg(
EM_uint128_t value)
04049 {
04050
EM_uint128_t tmp;
04051
04052
04053 value.
lo = ~value.
lo;
04054 value.
hi = ~value.
hi;
04055
04056 tmp.
lo = value.
lo + 1;
04057 tmp.
hi = value.
hi + (tmp.
lo < value.
lo);
04058
return (tmp);
04059 }
04060
04061
EM_uint128_t
04062 fp82_fp_U128_add(
EM_uint128_t value1,
04063
EM_uint128_t value2)
04064 {
04065
EM_uint128_t tmp;
04066
04067
04068 value2.
lo = value1.
lo + value2.
lo;
04069 value2.
hi = value1.
hi + value2.
hi;
04070
04071 tmp.
lo = 0;
04072 tmp.
hi = (value2.
lo < value1.
lo);
04073
04074
04075 tmp.
lo = value2.
lo;
04076 tmp.
hi += value2.
hi;
04077
return (tmp);
04078 }
04079
04080
EM_uint128_t
04081 fp82_fp_U128_bor(
EM_uint128_t value1,
EM_uint128_t value2)
04082 {
04083
EM_uint128_t tmp_res;
04084 tmp_res.
lo = value1.
lo | value2.
lo;
04085 tmp_res.
hi = value1.
hi | value2.
hi;
04086
return (tmp_res);
04087 }
04088
04089
EM_uint128_t
04090 fp82_fp_U128_band(
EM_uint128_t value1,
EM_uint128_t value2)
04091 {
04092
EM_uint128_t tmp_res;
04093 tmp_res.
lo = value1.
lo & value2.
lo;
04094 tmp_res.
hi = value1.
hi & value2.
hi;
04095
return (tmp_res);
04096 }
04097
04098
04099
04100
EM_boolean_t
04101 fp82_fp_U256_eq(
EM_uint256_t value1,
EM_uint256_t value2)
04102 {
04103
if ( (value1.
hh == value2.
hh)
04104 && (value1.
hl == value2.
hl )
04105 && (value1.
lh == value2.
lh )
04106 && (value1.
ll == value2.
ll ) )
04107
return (1);
04108
else
04109
return (0);
04110 }
04111
04112
04113
EM_uint256_t
04114 fp82_fp_U256_lsh(
EM_uint256_t value, EM_uint_t count)
04115 {
04116
EM_uint256_t tmp;
04117
if (count == 0) {
04118
return (value);
04119 }
else if (count >= 256) {
04120
return (U256_0);
04121
04122 }
else if (count > 192) {
04123 tmp.
ll = U64_0;
04124 tmp.
lh = U64_0;
04125 tmp.
hl = U64_0;
04126 tmp.
hh = (value.
ll<<(count-192));
04127
return (tmp);
04128 }
else if (count == 192) {
04129 tmp.
ll = U64_0;
04130 tmp.
lh = U64_0;
04131 tmp.
hl = U64_0;
04132 tmp.
hh = value.
ll;
04133
return (tmp);
04134 }
else if (count > 128) {
04135 tmp.
ll = U64_0;
04136 tmp.
lh = U64_0;
04137 tmp.
hl = (value.
ll<<(count-128));
04138 tmp.
hh = (value.
lh<<(count-128)) | (value.
ll>>(192-count));
04139
return (tmp);
04140 }
else if (count == 128) {
04141 tmp.
ll = U64_0;
04142 tmp.
lh = U64_0;
04143 tmp.
hl = value.
ll;
04144 tmp.
hh = value.
lh;
04145
return (tmp);
04146 }
else if (count > 64) {
04147 tmp.
ll = U64_0;
04148 tmp.
lh = (value.
ll<<(count-64));
04149 tmp.
hl = (value.
lh<<(count-64)) | (value.
ll>>(128-count)) ;
04150 tmp.
hh = (value.
hl<<(count-64)) | (value.
lh>>(128-count)) ;
04151
return (tmp);
04152 }
else if (count == 64) {
04153 tmp.
ll = 0;
04154 tmp.
lh = value.
ll;
04155 tmp.
hl = value.
lh;
04156 tmp.
hh = value.
hl;
04157
return (tmp);
04158 }
else if (count > 0) {
04159 tmp.
ll = (value.
ll<<count);
04160 tmp.
lh = (value.
lh<<count) | (value.
ll>>(64-count)) ;
04161 tmp.
hl = (value.
hl<<count) | (value.
lh>>(64-count)) ;
04162 tmp.
hh = (value.
hh<<(count)) | (value.
hl>>(64-count)) ;
04163
return (tmp);
04164 }
04165
return(U256_0);
04166
04167 }
04168
04169
EM_uint256_t
04170 fp82_fp_U256_rsh(
EM_uint256_t value, EM_uint_t count)
04171 {
04172
EM_uint256_t tmp;
04173
if (count == 0) {
04174
return (value);
04175 }
else if (count >= 256) {
04176
return (U256_0);
04177
04178 }
else if (count > 192) {
04179 tmp.
ll = (value.
hh>>(count-192));
04180 tmp.
lh = U64_0;
04181 tmp.
hl = U64_0;
04182 tmp.
hh = U64_0;
04183
return (tmp);
04184 }
else if (count == 192) {
04185 tmp.
ll = value.
hh;
04186 tmp.
lh = U64_0;
04187 tmp.
hl = U64_0;
04188 tmp.
hh = U64_0;
04189
return (tmp);
04190 }
else if (count > 128) {
04191 tmp.
ll = (value.
hl>>(count-128)) | (value.
hh<<(192-count));
04192 tmp.
lh = (value.
hh>>(count-128));
04193 tmp.
hl = U64_0;
04194 tmp.
hh = U64_0;
04195
return (tmp);
04196 }
else if (count == 128) {
04197 tmp.
ll = value.
hl;
04198 tmp.
lh = value.
hh;
04199 tmp.
hl = U64_0;
04200 tmp.
hh = U64_0;
04201
return (tmp);
04202 }
else if (count > 64) {
04203 tmp.
ll = (value.
lh>>(count-64)) | (value.
hl<<(128-count));
04204 tmp.
lh = (value.
hl>>(count-64)) | (value.
hh<<(128-count));
04205 tmp.
hl = (value.
hh>>(count-64));
04206 tmp.
hh = U64_0;
04207
return (tmp);
04208 }
else if (count == 64) {
04209 tmp.
ll = value.
lh;
04210 tmp.
lh = value.
hl;
04211 tmp.
hl = value.
hh;
04212 tmp.
hh = U64_0;
04213
return (tmp);
04214 }
else if (count > 0) {
04215 tmp.
ll = (value.
ll>>count) | (value.
lh<<(64-count));
04216 tmp.
lh = (value.
lh>>count) | (value.
hl<<(64-count));
04217 tmp.
hl = (value.
hl>>count) | (value.
hh<<(64-count));
04218 tmp.
hh = (value.
hh>>count);
04219
return (tmp);
04220 }
04221
return(U256_0);
04222
04223 }
04224
04225
EM_uint256_t
04226 fp82_fp_U256_inc(
EM_uint256_t value)
04227 {
04228
EM_uint256_t tmp;
04229
04230
04231 tmp.
ll = value.
ll + 1;
04232 tmp.
lh = value.
lh + (tmp.
ll < value.
ll);
04233 tmp.
hl = value.
hl + (tmp.
lh < value.
lh);
04234 tmp.
hh = value.
hh + (tmp.
hl < value.
hl);
04235
return (tmp);
04236 }
04237
04238
static INLINE EM_uint256_t
04239 fp_U256_neg(
EM_uint256_t value)
04240 {
04241
EM_uint256_t tmp;
04242
04243
04244 value.
ll = ~value.
ll;
04245 value.
lh = ~value.
lh;
04246 value.
hl = ~value.
hl;
04247 value.
hh = ~value.
hh;
04248
04249 tmp.
ll = value.
ll + 1;
04250 tmp.
lh = value.
lh + (tmp.
ll < value.
ll);
04251 tmp.
hl = value.
hl + (tmp.
lh < value.
lh);
04252 tmp.
hh = value.
hh + (tmp.
hl < value.
hl);
04253
return (tmp);
04254 }
04255
04256
static INLINE EM_uint256_t
04257 fp_U256_add(
EM_uint256_t value1,
EM_uint256_t value2)
04258 {
04259
EM_uint256_t tmp;
04260
04261
04262 value2.
ll = value1.
ll + value2.
ll;
04263 value2.
lh = value1.
lh + value2.
lh;
04264 value2.
hl = value1.
hl + value2.
hl;
04265 value2.
hh = value1.
hh + value2.
hh;
04266
04267 tmp.
ll = 0;
04268 tmp.
lh = (value2.
ll < value1.
ll);
04269 tmp.
hl = (value2.
lh < value1.
lh);
04270 tmp.
hh = (value2.
hl < value1.
hl);
04271
04272
04273 tmp.
ll = value2.
ll;
04274 tmp.
lh += value2.
lh;
04275 tmp.
hl += value2.
hl + (tmp.
lh < value2.
lh);
04276 tmp.
hh += value2.
hh + (tmp.
hl < value2.
hl);
04277
04278
return (tmp);
04279 }
04280
04281
04282
04283
INLINE EM_uint128_t
04284 fp_U64_to_U128(EM_uint64_t value)
04285 {
04286
EM_uint128_t tmp;
04287 tmp.
lo = value;
04288 tmp.
hi = U64_0;
04289
return (tmp);
04290 }
04291
04292
INLINE EM_uint64_t
04293 fp_U128_to_U64(
EM_uint128_t value)
04294 {
04295
EM_uint64_t tmp;
04296 tmp = value.
lo;
04297
return (tmp);
04298 }
04299
04300
static INLINE EM_uint256_t
04301 fp_U64_to_U256(EM_uint64_t value)
04302 {
04303
EM_uint256_t tmp;
04304 tmp.
ll = value;
04305 tmp.
lh = U64_0;
04306 tmp.
hl = U64_0;
04307 tmp.
hh = U64_0;
04308
return (tmp);
04309 }
04310
04311
static INLINE EM_uint64_t
04312 fp_U256_to_U64(
EM_uint256_t value)
04313 {
04314
EM_uint64_t tmp;
04315 tmp = value.
ll;
04316
return (tmp);
04317 }
04318
04319
EM_uint256_t
04320 fp82_fp_U128_to_U256(
EM_uint128_t value)
04321 {
04322
EM_uint256_t tmp;
04323 tmp.
ll = value.
lo;
04324 tmp.
lh = value.
hi;
04325 tmp.
hl = U64_0;
04326 tmp.
hh = U64_0;
04327
return (tmp);
04328 }
04329
04330
static INLINE EM_uint128_t
04331 fp_U256_to_U128(
EM_uint256_t value)
04332 {
04333
EM_uint128_t tmp;
04334 tmp.
lo = value.
ll;
04335 tmp.
hi = value.
lh;
04336
return (tmp);
04337 }
04338